mux_4_1_when_else

-- PROJETO: mux_4_1_when_else
-- ENTRADA A, B, C, D, sel1, sel2 (tipo bit)
-- SAIDA: S (tipo bit)
-- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL FERNANDES
-- CRIACAO: 22/11/2019
-- ALTERACAO: 22/11/2019
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Entity mux_4_1_when_else is
Port(A, B, C, D : IN BIT;
     sel1, sel2 : IN BIT;
              S : OUT BIT);
end mux_4_1_when_else;

Architecture teste of mux_4_1_when_else is
begin
S <= A WHEN (sel1 = '0' AND sel2 = '0') ELSE
     B WHEN (sel1 = '0' AND sel2 = '1') ELSE
     C WHEN (sel1 = '1' AND sel2 = '0') ELSE
     D;
end teste;