rom2

----------------------------------------------------------------------------------
-- Logicko projektovanje racunarskih sistema 1
-- 2011/2012
-- Lab 7
--
-- Instruction ROM
--
-- author: Branislav Nikolic
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity instr_rom is
    Port ( iA : in  STD_LOGIC_VECTOR (4 downto 0);
           oQ : out  STD_LOGIC_VECTOR (14 downto 0));
end instr_rom;

architecture Behavioral of instr_rom is

    -- ALU instructions --
    constant cMOV : std_logic_vector(5 downto 0) := "000000";
    constant cADD : std_logic_vector(5 downto 0) := "000001";
    constant cSUB : std_logic_vector(5 downto 0) := "000010";
    constant cAND : std_logic_vector(5 downto 0) := "000011";
    constant cOR : std_logic_vector(5 downto 0) := "000100";
    constant cNOT : std_logic_vector(5 downto 0) := "000101";
    constant cINC : std_logic_vector(5 downto 0) := "000110";
    constant cDEC : std_logic_vector(5 downto 0) := "000111";
    constant cSHL : std_logic_vector(5 downto 0) := "001000";
    constant cSHR : std_logic_vector(5 downto 0) := "001001";
    constant cASHL : std_logic_vector(5 downto 0) := "001010";
    constant cASHR : std_logic_vector(5 downto 0) := "001011";
     constant cJMP:  std_logic_vector(5 downto 0) :="010000";
     constant cJMPZ:  std_logic_vector(5 downto 0) :="010001";
     constant cJMPS:  std_logic_vector(5 downto 0) :="010010";
    constant cJMC:  std_logic_vector(5 downto 0) :="010011";
     constant cJMPNZ:  std_logic_vector(5 downto 0) :="010101";
     constant cJMPNS:  std_logic_vector(5 downto 0) :="010110";
    constant cJMNC:  std_logic_vector(5 downto 0) :="010111";

    -- Other instructions --
    constant cLD : std_logic_vector(5 downto 0) := "100000";
    constant cST : std_logic_vector(5 downto 0) := "110000";

    -- Registers --
    constant cR0 : std_logic_vector(2 downto 0) := "000";
    constant cR1 : std_logic_vector(2 downto 0) := "001";
    constant cR2 : std_logic_vector(2 downto 0) := "010";
    constant cR3 : std_logic_vector(2 downto 0) := "011";
    constant cR4 : std_logic_vector(2 downto 0) := "100";
    constant cR5 : std_logic_vector(2 downto 0) := "101";
    constant cR6 : std_logic_vector(2 downto 0) := "110";
    constant cR7 : std_logic_vector(2 downto 0) := "111";
    constant cRX : std_logic_vector(2 downto 0) := "---"; -- reg field not used

begin
 process(iA)begin
    case (iA)is

--definition parameters:
    when "00000"=>  oQ<= cLD &cR1 &cRX &cR1;
    when "00001" =>         oQ<= cLD &cR2 &cRX &cR2;
    when "00010" =>         oQ<= cLD &cR3 &cRX &cR3;
    when"00011" =>      oQ<= cINC &cR1 &cR1 &cRX;
    when"00100" =>      oQ<= cASHL &cR1 &cR1 &cRX;
    when "00101" =>         oQ<= cASHL &cR1 &cR1 &cRX; --R1=4
    when "00110" =>         oQ<= cINC &cR2 &cR2 &cRX; --R2=1
    when "00111" =>         oQ<= cINC &cR3 &cR3 &cRX;
    when "01000" =>         oQ<= cASHL &cR3 &cR3 &cRX;
    when "01001"=>      oQ<= cASHL &cR3 &cR3 &cRX;
    when "01010"=>      oQ<= cASHL &cR3 &cR3 &cRX;
    when "01011"=>      oQ<= cDEC &cR3 &cR3 &cRX; --R3=7

--loop:
    when "01100"=>      oQ<= cSUB &cR0 &cR2 &cR1;
    when "01101"=>              oQ<= cJMPS &"000010000";
--do_if_true(R4<-7)
        when "01110"=>  oQ<= cMOV &cR4 &cR3 &cRX;
        when "01111" =>     oQ<= cJMP &"000010011";
--do_if_false
        when "10000" => oQ<= cDEC &cR1 &cR1 &cRX;
        when "10001" => oQ<= cINC &cR2 &cR2 &cRX;
        when "10010"=>  oQ<= cJMP &"000001100"; --jmp to loop
--end(anything stupid)
        when "10011"=> oQ<= cMOV &cR0 &cR0 &cRX;

    when others => oQ<= (others => '0');

    end case;
end process;


end Behavioral;