library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control is
port(
            clk : in std_logic;
            IR : in signed(15 downto 0);
            reset, C, Z, S, INT : in std_logic;
            Salu, Sbb, Sbc, Sba : out bit_vector(3 downto 0);
            Sid : out bit_vector(2 downto 0);
            Sa : out bit_vector(1 downto 0);
            LDF, Smar, Smbr, WR, RD, INTA, MIO : out bit
);
end entity;

architecture rtl of control is
type state_type is (    fetch, decode, mov1, mov2, add1, add2, sub1, sub2, st4s1, st4s2, st2s1, st2s2,
                            l2b, l4b, and1, and2, and3, beq );
signal state : state_type;
begin
process (clk, reset)
begin
    if reset = '1' then
    state <= fetch;
    elsif (clk'event and clk='1') then
    case state is
        when fetch => state <= decode;
        when decode => case IR(15 downto 13) is
            when "000" => state <= fetch;
            when "001" => case IR(12 downto 8) is
                when "00000" => state <= mov1;
                when "00001" => state <= mov2;
                when "00010" => state <= add1;
                when "00011" => state <= add2;
                when "00100" => state <= sub1;
                when "00101" => state <= sub2;
                when "00110" => state <= st4s1;
                when "00111" => state <= st4s2;
                when "01000" => state <= st2s1;
                when "01001" => state <= st2s2;
                when "01010" => state <= l2b;
                when "01011" => state <= l4b;
                when "01100" => state <= and1;
                when "01101" => state <= and2;
                when "01110" => state <= and3;
                when "01111" => state <= beq;

                when others => state <= fetch;
            end case;
            when others => state <= fetch;
     end case;
     end case;

    end if;
    end process;
    process (state)
    begin
    case state is
    when fetch => Sa <= "01"; Sbb <= "0000"; Sba <= "0000"; Sid <="001"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '0'; WR <='0'; RD <='1'; Salu <="0000"; LDF <='0'; INTA <='0';
    when decode => Sa <= "00"; Sbb <= "0000"; Sba <= "0000"Sid <="000"; Sbc <="0000"; MIO <='1'; Smar <='0'; Smbr <= '0'; WR <='0'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when mov1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000";  Sid <="000";  Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when mov2 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when add1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0010"; LDF <='0'; INTA <='0';
    when add2 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0010"; LDF <='0'; INTA <='0';
    when sub1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0011"; LDF <='0'; INTA <='0';
    when sub2 =>Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0011"; LDF <='0'; INTA <='0';
    when st4s1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when st4s2 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when st2s1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when st2s2 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    when l2b => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0100"; LDF <='0'; INTA <='0';
    when l4b => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0101"; LDF <='0'; INTA <='0';
    when and1 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0110"; LDF <='0'; INTA <='0';
    when and2 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0110"; LDF <='0';INTA <='0';
    when and3 => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0110"; LDF <='0'; INTA <='0';
    when beq => Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <="011"; Sbc <="0000"; MIO <='1'; Smar <='1'; Smbr <= '1'; WR <='1'; RD <='0'; Salu <="0111"; LDF <='0'; INTA <='0';
    when others => Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <="000"; Sbc <="0000"; MIO <='1'; Smar <='0'; Smbr <= '0'; WR <='0'; RD <='0'; Salu <="0000"; LDF <='0'; INTA <='0';
    end case;
end process;
end rtl;