Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
- entity lr4 is
- generic(aw:positive:=8; dw:positive:=128); -- 2^8=256, 256x128
- Port(
- clk ,we ,en : in std_logic;
- addr : in std_logic_vector(aw-1 downto 0);
- di : in std_logic_vector(dw-1 downto 0);
- do : out std_logic_vector(dw-1 downto 0)
- );
- end lr4;
- architecture Behavioral of lr4 is
- type ram_type is array (0 to 2**aw-1 ) of std_logic_vector (dw-1 downto 0);
- signal RAM: ram_type :=(
- x"99",x"88",x"77",x"66",
- x"55",x"44",x"33",x"22",
- x"11",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00",
- x"00",x"00",x"00",x"00"
- );
- begin
- process (clk)
- begin
- if rising_edge(clk) then
- if en = '1' then
- if we = '1' then --write
- RAM(conv_integer(addr)) <= di;
- end if;
- do <= RAM(conv_integer(addr));
- end if;
- end if;
- end process;
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement