library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

-- internal rendering is done via block ram so 320x240x4 mode supported only

-- modes supported
-- mode: 0 - 640x480@60Hz max number of pixels

entity VGA is
    generic (
        g_Mode : natural := 0
    );
    port
    (
        CLOCK         : in std_logic;

        VGA_HSYNC     : out std_logic;
        VGA_VSYNC     : out std_logic;

        VGA_R        : out std_logic_vector (0 to 7);
        VGA_G        : out std_logic_vector (0 to 7);
        VGA_B        : out std_logic_vector (0 to 7);

        VGA_CLOCK     : out std_logic;
        NOT_RENDERING : out std_logic;

        WRITE_X       : in  integer range 0 to 320 := 0;
        WRITE_Y       : in  integer range 0 to 240 := 0;
        WRITE_SIGNAL  : in  std_logic := '0';
        WRITE_COLOR   : in  std_logic_vector (1 downto 0) := "00";
        WROTE             : out std_logic
    );
end VGA;

architecture RTL of VGA is

    subtype t_Color is std_logic_vector (1 downto 0);
    type t_RenderBuffer is array(0 to (320*240)-1) of t_Color;

    -- PLL 108 MHz clock
    component ecomputer is
      port (
            vga_pll_outclk0_clk : out std_logic;        -- clk
            vga_pll_refclk_clk  : in  std_logic := 'X'; -- clk
            vga_pll_reset_reset : in  std_logic := 'X'  -- reset
      );
    end component ecomputer;

    signal w_VgaClock    : std_logic;
    signal w_Reset       : std_logic := '0';

    signal r_Buffer      : t_RenderBuffer := (others => "00");

    signal w_R              : std_logic_vector (0 to 7);
    signal w_G              : std_logic_vector (0 to 7);
    signal w_B              : std_logic_vector (0 to 7);

    signal w_VColumns   : integer range 0 to 4096;
    signal w_VRows          : integer range 0 to 4096;
    signal w_Rendering   : std_logic;

    signal r_Hpos        : integer range 0 to 4096 := 0;
    signal r_Vpos        : integer range 0 to 4096 := 0;
    signal w_Divider     : integer range 1 to 128  := 1;

    -- fifo management

    signal w_FifoWriteF  : std_logic;
    signal w_FifoWriteB  : std_logic;
    signal w_FifoReadAv  : std_logic;
    signal w_FifoWriteD  : std_logic_vector (19 downto 0);
    signal w_FifoReadRq  : std_logic;
    signal w_FifoReadEm  : std_logic;
    signal w_FifoReadQ   : std_logic_vector (19 downto 0);

begin

    ce : component ecomputer
        port map (
            vga_pll_outclk0_clk => w_VgaClock,
            vga_pll_refclk_clk  => CLOCK,
            vga_pll_reset_reset => w_Reset
        );

    e_Fifo : entity work.VGAFifo
        port map (wrfull => w_FifoWriteF, wrclk => CLOCK, wrreq => WRITE_SIGNAL, data => w_FifoWriteD,
              rdclk => w_VgaClock, rdempty => w_FifoReadEm, rdreq => w_FifoReadRq, q => w_FifoReadQ);

    modeselect_gen : if g_Mode = 0 generate
        w_Divider <= 2;
    end generate modeselect_gen;

    e_Sync : entity work.VGASync
        port map (
            CLOCK => w_VgaClock,
            HSYNC => VGA_HSYNC, VSYNC => VGA_VSYNC,
            R => w_R, G => w_G, B => w_B,
            VCOLUMNS => w_VColumns, VROWS => w_VRows, RENDERING_PIXELS => w_Rendering
        );

    VGA_CLOCK <= w_VgaClock;

    w_DrawToBuffer : process (CLOCK) is begin

        if rising_edge(CLOCK) then

            if WRITE_SIGNAL = '1' then
                if w_FifoWriteF = '1' then
                    w_FifoWriteD <= WRITE_COLOR & (std_logic_vector(to_unsigned((320*WRITE_X) + WRITE_Y, 17))) & "0";
                end if;
            end if;

        end if;

    end process w_DrawToBuffer;

    w_DrawResult : process (w_FifoWriteF, WRITE_SIGNAL) is begin
        WROTE <= w_FifoWriteF and WRITE_SIGNAL;
    end process w_DrawResult;

    w_DrawBuffer : process (w_VgaClock) is begin

        if rising_edge(w_VgaClock) then

            if w_FifoReadEm = '0' then
                w_FifoReadRq <= '1';
                r_Buffer(to_integer(unsigned(w_FifoReadQ(17 downto 1))))(to_integer(unsigned(w_FifoReadQ(19 downto 17))));
            end if;

            if w_Rendering = '1' then
                if r_Hpos < w_VColumns-1 then
                    r_Hpos <= r_Hpos + 1;
                else
                    r_Hpos <= 0;
                    if r_Vpos < w_VRows-1 then
                        r_Vpos <= r_Vpos + 1;
                    else
                        r_Vpos <= 0;
                    end if;
                end if;

                case r_Buffer((((r_Vpos - (r_Vpos mod w_Divider)) / w_Divider) * (w_VColumns / w_Divider)) + ((r_Hpos - (r_Hpos mod w_Divider)) / w_Divider)) is
                    when "00" =>
                        -- black
                        VGA_R <= "00000000";
                        VGA_G <= "00000000";
                        VGA_B <= "00000000";
                    when "01" =>
                        -- matrix green
                        VGA_R <= "01110001";
                        VGA_G <= "11111111";
                        VGA_B <= "01001110";
                    when "10" =>
                        -- complementary to matrix green
                        VGA_R <= "11111111";
                        VGA_G <= "01001110";
                        VGA_B <= "01110001";
                    when "11" =>
                        -- white
                        VGA_R <= "11111111";
                        VGA_G <= "11111111";
                        VGA_B <= "11111111";
                    when others => null;
                end case;
            else
                VGA_R <= w_R;
                VGA_G <= w_G;
                VGA_B <= w_B;
            end if;

        end if;

    end process w_DrawBuffer;

    NOT_RENDERING <= w_Rendering;

end architecture RTL;