cursofpgavhdl

meio_somador_1bit

Nov 28th, 2019
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VHDL 0.52 KB | None | 0 0
  1. -- PROJETO: meio_somador_1bit
  2. -- ENTRADA A, B (tipo bit)
  3. -- SAIDA: S, COUT (tipo bit)
  4. -- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL TERFERNANDES
  5. -- CRIACAO: 05/12/2018
  6. -- ALTERACAO: 22/11/2019
  7. ----------------------------------------------------------
  8. entity meio_somador_1bit is
  9.     port (A, B: in bit;
  10.        S, COUT: out bit);
  11. end meio_somador_1bit;
  12. ----------------------------------------------------------
  13. architecture dataflow of meio_somador_1bit is
  14. begin
  15.     S <= A xor B;
  16.     COUT <= A and B;
  17. end dataflow;
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