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SallatielFernandes

CI_74HC04_dataflow

Nov 22nd, 2019
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VHDL 0.62 KB | None | 0 0
  1. --PROJETO: CI_74HC04_dataflow
  2. --ENTRADAS: A, B, C, D (in bit)
  3. --SAIDAS: SA, SB, SC, SD (out bit)
  4. --AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL FERNANDES
  5. --CRIACAO: 30/01/2018
  6. --ATUALIZACAO: 22/11/2019
  7. ----------------------------------------------------------
  8. entity CI_74HC04_dataflow is
  9.     port (A, B, C, D: in bit;
  10.       SA, SA, SC, SD: out bit);
  11. end CI_74HC04_dataflow ;
  12. ----------------------------------------------------------
  13. architecture dataflow of CI_74HC04_dataflow is
  14. begin
  15.     SA <= not A;
  16.     SB <= not B;
  17.     SC <= not C;
  18.     SD <= not D;
  19. end dataflow;
  20. ----------------------------------------------------------
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