library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Domaci4_tb is
end entity;

architecture Behavioral of Domaci4_tb is
    signal sCLK : std_logic;
    signal sRST : std_logic;
    signal sOK : std_logic;
    signal sHAZ : std_logic;
    signal sRED : std_logic;
    signal sGREEN : std_logic;
    signal sYELLOW : std_logic;

component Domaci4
port(iCLK : in std_logic;
      iRST : in std_logic;
      iOK : in std_logic;
      iHAZ : in std_logic;
      oRED : out std_logic;
      oYELLOW : out std_logic;
      oGREEN : out std_logic
        );
end component;

    constant iCLK_period : time := 10 ns;

begin
    uut: Domaci4 port map(
                        iCLK => sCLK,
                        iRST => sRST,
                        iOK => sOK,
                        iHAZ => sHAZ,
                        oRED => sRED,
                        oYELLOW => sYELLOW,
                        oGREEN => sGREEN
                                    );
iCLK_process : process
begin
    sCLK <= '0';
    wait for iCLK_period/2;
    sCLK <= '1';
    wait for iCLK_period/2;
end process;

stimulus : process
begin
    sOK <= '0';
    sHAZ <= '0';
    sRST <= '1';
    wait for 5.25 * iCLK_period;
    sRST <= '0';
    wait for 2.25 * iCLK_period;
    sOK <= '1';
    wait for 2.25 * iCLK_period;
    sOK <= '0';
    wait for 29000 ns;
    sHAZ <= '1';
    wait for 2.25 * iCLK_period;
    sHAZ <= '0';
    wait for 130000 ns;
    sOK <= '1';
    wait for 2.25 * iCLK_period;
    sOK <= '0';
    wait for 60000 ns;
    sRST <= '1';
    wait for 5.25 * iCLK_period;
    sRST <= '0';
    wait;

end process stimulus;
end architecture;