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  1. module top(input clk, output [7:0] led);
  2. reg [7:0] rst_cnt;
  3.  
  4.  
  5. always @(posedge clk)
  6. if (!rst_cnt[7])
  7. rst_cnt <= rst_cnt + 1;
  8.  
  9. wire rst = !rst_cnt[7];
  10. wire tx_pclk, rx_pclk;
  11. reg [30:0] ctr;
  12. reg comma;
  13.  
  14. always @(posedge tx_pclk) begin
  15. ctr <= ctr + 1'b1;
  16. comma <= &(ctr[9:1]);
  17. end
  18.  
  19. wire [7:0] txd = comma ? 8'hbc : ctr[30:23];
  20. wire [7:0] rxd;
  21. assign led = ~rxd;
  22.  
  23. wire tx_pcs_rst = rst, rx_pcs_rst = rst, rx_ser_rst = rst, tx_ser_rst = rst, dual_rst = rst, serdes_dual_rst = rst;
  24. wire tx_pwrup = 1'b1, rx_pwrup = 1'b1, serdes_pdb = 1'b1;
  25. wire rx_los_lol, rx_cdr_lol;
  26.  
  27. (* BEL="X42/Y71/DCU" *)
  28. DCUA DCU0_inst (
  29. .CH0_HDINP(), .CH1_HDINP(),
  30. .CH1_RX_REFCLK(clk),
  31. .CH1_FF_RXI_CLK(rx_pclk), .CH1_FF_RX_PCLK(rx_pclk),
  32. .CH1_FF_TXI_CLK(tx_pclk), .CH1_FF_TX_PCLK(tx_pclk),
  33. .CH1_FF_TX_D_0(txd[0]), .CH1_FF_TX_D_1(txd[1]), .CH1_FF_TX_D_2(txd[2]), .CH1_FF_TX_D_3(txd[3]),
  34. .CH1_FF_TX_D_4(txd[4]), .CH1_FF_TX_D_5(txd[5]), .CH1_FF_TX_D_6(txd[6]), .CH1_FF_TX_D_7(txd[7]),
  35. .CH1_FF_TX_D_8(comma), .CH1_FF_TX_D_9(1'b0) , .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(1'b0),
  36. .CH1_FFC_EI_EN(1'b0), .CH1_FFC_SIGNAL_DETECT(1'b1), .CH1_FFC_LANE_TX_RST(tx_pcs_rst), .CH1_FFC_LANE_RX_RST(rx_pcs_rst),
  37. .CH1_FFC_RRST(rx_ser_rst), .CH1_FFC_TXPWDNB(tx_pwrup), .CH1_FFC_RXPWDNB(rx_pwrup), .D_FFC_DUAL_RST(dual_rst),
  38. .D_FFC_MACRO_RST(serdes_dual_rst), .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_ser_rst),
  39. .CH1_FF_RX_D_0(rxd[0]), .CH1_FF_RX_D_1(rxd[1]), .CH1_FF_RX_D_2(rxd[2]), .CH1_FF_RX_D_3(rxd[3]),
  40. .CH1_FF_RX_D_4(rxd[4]), .CH1_FF_RX_D_5(rxd[5]), .CH1_FF_RX_D_6(rxd[6]), .CH1_FF_RX_D_7(rxd[7]),
  41. .CH1_FFS_RLOS(rx_los_lol), .CH1_FFS_RLOL(rx_cdr_lol),
  42. .D_REFCLKI(clk)
  43. );
  44.  
  45. defparam DCU0_inst.D_MACROPDB = "0b1";
  46. defparam DCU0_inst.D_IB_PWDNB = "0b1";
  47. defparam DCU0_inst.D_XGE_MODE = "0b0";
  48. defparam DCU0_inst.D_LOW_MARK = "0d4";
  49. defparam DCU0_inst.D_HIGH_MARK = "0d12";
  50. defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
  51. defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
  52. defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
  53. defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
  54. defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
  55. defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
  56. defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
  57. defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
  58. defparam DCU0_inst.CH1_UC_MODE = "0b1";
  59. defparam DCU0_inst.CH1_PCIE_MODE = "0b0";
  60. defparam DCU0_inst.CH1_RIO_MODE = "0b0";
  61. defparam DCU0_inst.CH1_WA_MODE = "0b1";
  62. defparam DCU0_inst.CH1_INVERT_RX = "0b0";
  63. defparam DCU0_inst.CH1_INVERT_TX = "0b0";
  64. defparam DCU0_inst.CH1_PRBS_SELECTION = "0b0";
  65. defparam DCU0_inst.CH1_GE_AN_ENABLE = "0b0";
  66. defparam DCU0_inst.CH1_PRBS_LOCK = "0b0";
  67. defparam DCU0_inst.CH1_PRBS_ENABLE = "0b0";
  68. defparam DCU0_inst.CH1_ENABLE_CG_ALIGN = "0b1";
  69. defparam DCU0_inst.CH1_TX_GEAR_MODE = "0b0";
  70. defparam DCU0_inst.CH1_RX_GEAR_MODE = "0b0";
  71. defparam DCU0_inst.CH1_PCS_DET_TIME_SEL = "0b00";
  72. defparam DCU0_inst.CH1_PCIE_EI_EN = "0b0";
  73. defparam DCU0_inst.CH1_TX_GEAR_BYPASS = "0b0";
  74. defparam DCU0_inst.CH1_ENC_BYPASS = "0b0";
  75. defparam DCU0_inst.CH1_SB_BYPASS = "0b0";
  76. defparam DCU0_inst.CH1_RX_SB_BYPASS = "0b0";
  77. defparam DCU0_inst.CH1_WA_BYPASS = "0b0";
  78. defparam DCU0_inst.CH1_DEC_BYPASS = "0b0";
  79. defparam DCU0_inst.CH1_CTC_BYPASS = "0b1";
  80. defparam DCU0_inst.CH1_RX_GEAR_BYPASS = "0b0";
  81. defparam DCU0_inst.CH1_LSM_DISABLE = "0b0";
  82. defparam DCU0_inst.CH1_MIN_IPG_CNT = "0b11";
  83. defparam DCU0_inst.CH1_UDF_COMMA_MASK = "0x3ff";
  84. defparam DCU0_inst.CH1_UDF_COMMA_A = "0x283";
  85. defparam DCU0_inst.CH1_UDF_COMMA_B = "0x17C";
  86. defparam DCU0_inst.CH1_RX_DCO_CK_DIV = "0b000";
  87. defparam DCU0_inst.CH1_RCV_DCC_EN = "0b0";
  88. defparam DCU0_inst.CH1_TPWDNB = "0b1";
  89. defparam DCU0_inst.CH1_RATE_MODE_TX = "0b0";
  90. defparam DCU0_inst.CH1_RTERM_TX = "0d19";
  91. defparam DCU0_inst.CH1_TX_CM_SEL = "0b00";
  92. defparam DCU0_inst.CH1_TDRV_PRE_EN = "0b0";
  93. defparam DCU0_inst.CH1_TDRV_SLICE0_SEL = "0b01";
  94. defparam DCU0_inst.CH1_TDRV_SLICE1_SEL = "0b00";
  95. defparam DCU0_inst.CH1_TDRV_SLICE2_SEL = "0b01";
  96. defparam DCU0_inst.CH1_TDRV_SLICE3_SEL = "0b01";
  97. defparam DCU0_inst.CH1_TDRV_SLICE4_SEL = "0b00";
  98. defparam DCU0_inst.CH1_TDRV_SLICE5_SEL = "0b00";
  99. defparam DCU0_inst.CH1_TDRV_SLICE0_CUR = "0b011";
  100. defparam DCU0_inst.CH1_TDRV_SLICE1_CUR = "0b000";
  101. defparam DCU0_inst.CH1_TDRV_SLICE2_CUR = "0b11";
  102. defparam DCU0_inst.CH1_TDRV_SLICE3_CUR = "0b10";
  103. defparam DCU0_inst.CH1_TDRV_SLICE4_CUR = "0b00";
  104. defparam DCU0_inst.CH1_TDRV_SLICE5_CUR = "0b00";
  105. defparam DCU0_inst.CH1_TDRV_DAT_SEL = "0b00";
  106. defparam DCU0_inst.CH1_TX_DIV11_SEL = "0b0";
  107. defparam DCU0_inst.CH1_RPWDNB = "0b1";
  108. defparam DCU0_inst.CH1_RATE_MODE_RX = "0b0";
  109. defparam DCU0_inst.CH1_RX_DIV11_SEL = "0b0";
  110. defparam DCU0_inst.CH1_SEL_SD_RX_CLK = "0b1";
  111. defparam DCU0_inst.CH1_FF_RX_H_CLK_EN = "0b0";
  112. defparam DCU0_inst.CH1_FF_RX_F_CLK_DIS = "0b0";
  113. defparam DCU0_inst.CH1_FF_TX_H_CLK_EN = "0b0";
  114. defparam DCU0_inst.CH1_FF_TX_F_CLK_DIS = "0b0";
  115. defparam DCU0_inst.CH1_TDRV_POST_EN = "0b0";
  116. defparam DCU0_inst.CH1_TX_POST_SIGN = "0b0";
  117. defparam DCU0_inst.CH1_TX_PRE_SIGN = "0b0";
  118. defparam DCU0_inst.CH1_REQ_LVL_SET = "0b00";
  119. defparam DCU0_inst.CH1_REQ_EN = "0b1";
  120. defparam DCU0_inst.CH1_RTERM_RX = "0d22";
  121. defparam DCU0_inst.CH1_RXTERM_CM = "0b11";
  122. defparam DCU0_inst.CH1_PDEN_SEL = "0b1";
  123. defparam DCU0_inst.CH1_RXIN_CM = "0b11";
  124. defparam DCU0_inst.CH1_LEQ_OFFSET_SEL = "0b0";
  125. defparam DCU0_inst.CH1_LEQ_OFFSET_TRIM = "0b000";
  126. defparam DCU0_inst.CH1_RLOS_SEL = "0b1";
  127. defparam DCU0_inst.CH1_RX_LOS_LVL = "0b100";
  128. defparam DCU0_inst.CH1_RX_LOS_CEQ = "0b11";
  129. defparam DCU0_inst.CH1_RX_LOS_HYST_EN = "0b0";
  130. defparam DCU0_inst.CH1_RX_LOS_EN = "0b1";
  131. defparam DCU0_inst.CH1_LDR_RX2CORE_SEL = "0b0";
  132. defparam DCU0_inst.CH1_LDR_CORE2TX_SEL = "0b0";
  133. //defparam DCU0_inst.D_TX_MAX_RATE = "2.5";
  134. //defparam DCU0_inst.CH1_CDR_MAX_RATE = "2.5";
  135. //defparam DCU0_inst.CH1_TXAMPLITUDE = "0d600";
  136. //defparam DCU0_inst.CH1_TXDEPRE = "DISABLED";
  137. //defparam DCU0_inst.CH1_TXDEPOST = "DISABLED";
  138. //defparam DCU0_inst.CH1_PROTOCOL = "G8B10B";
  139. defparam DCU0_inst.D_ISETLOS = "0d0";
  140. defparam DCU0_inst.D_SETIRPOLY_AUX = "0b10";
  141. defparam DCU0_inst.D_SETICONST_AUX = "0b01";
  142. defparam DCU0_inst.D_SETIRPOLY_CH = "0b10";
  143. defparam DCU0_inst.D_SETICONST_CH = "0b10";
  144. defparam DCU0_inst.D_REQ_ISET = "0b001";
  145. defparam DCU0_inst.D_PD_ISET = "0b00";
  146. defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
  147. defparam DCU0_inst.CH1_CDR_CNT4SEL = "0b00";
  148. defparam DCU0_inst.CH1_CDR_CNT8SEL = "0b00";
  149. defparam DCU0_inst.CH1_DCOATDCFG = "0b00";
  150. defparam DCU0_inst.CH1_DCOATDDLY = "0b00";
  151. defparam DCU0_inst.CH1_DCOBYPSATD = "0b1";
  152. defparam DCU0_inst.CH1_DCOCALDIV = "0b000";
  153. defparam DCU0_inst.CH1_DCOCTLGI = "0b011";
  154. defparam DCU0_inst.CH1_DCODISBDAVOID = "0b0";
  155. defparam DCU0_inst.CH1_DCOFLTDAC = "0b00";
  156. defparam DCU0_inst.CH1_DCOFTNRG = "0b001";
  157. defparam DCU0_inst.CH1_DCOIOSTUNE = "0b010";
  158. defparam DCU0_inst.CH1_DCOITUNE = "0b00";
  159. defparam DCU0_inst.CH1_DCOITUNE4LSB = "0b010";
  160. defparam DCU0_inst.CH1_DCOIUPDNX2 = "0b1";
  161. defparam DCU0_inst.CH1_DCONUOFLSB = "0b100";
  162. defparam DCU0_inst.CH1_DCOSCALEI = "0b01";
  163. defparam DCU0_inst.CH1_DCOSTARTVAL = "0b010";
  164. defparam DCU0_inst.CH1_DCOSTEP = "0b11";
  165. defparam DCU0_inst.CH1_BAND_THRESHOLD = "0d0";
  166. defparam DCU0_inst.CH1_AUTO_FACQ_EN = "0b1";
  167. defparam DCU0_inst.CH1_AUTO_CALIB_EN = "0b1";
  168. defparam DCU0_inst.CH1_CALIB_CK_MODE = "0b0";
  169. defparam DCU0_inst.CH1_REG_BAND_OFFSET = "0d0";
  170. defparam DCU0_inst.CH1_REG_BAND_SEL = "0d0";
  171. defparam DCU0_inst.CH1_REG_IDAC_SEL = "0d0";
  172. defparam DCU0_inst.CH1_REG_IDAC_EN = "0b0";
  173. defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
  174. defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
  175. defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
  176. defparam DCU0_inst.D_CMUSETZGM = "0b000";
  177. defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
  178. defparam DCU0_inst.D_CMUSETP1GM = "0b000";
  179. defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
  180. defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
  181. defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
  182. defparam DCU0_inst.D_CMUSETICP4P = "0b01";
  183. defparam DCU0_inst.D_CMUSETBIASI = "0b00";
  184. defparam DCU0_inst.D_SETPLLRC = "0d1";
  185. defparam DCU0_inst.CH1_RX_RATE_SEL = "0d10";
  186. defparam DCU0_inst.D_REFCK_MODE = "0b100";
  187. defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000";
  188. defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
  189. defparam DCU0_inst.D_RG_EN = "0b0";
  190. defparam DCU0_inst.D_RG_SET = "0b00";
  191.  
  192. reg [27:0] rx_hb, tx_hb;
  193.  
  194. always @(posedge tx_pclk) tx_hb <= tx_hb + 1'b1;
  195. always @(posedge rx_pclk) rx_hb <= rx_hb + 1'b1;
  196.  
  197. // assign disp = {10'h3FF, rx_los_lol, rx_cdr_lol, tx_hb[27], rx_hb[27]};
  198.  
  199. endmodule
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