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- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- --TODO implement video on/off to this controller--
- entity GAME_VGA is
- port(
- in_clk_50 : in std_logic; -- vga clock
- in_clk_28: in std_logic; -- clock to be divided to 1hz
- out_xSync : out std_logic; -- horizontal sync
- out_ySync : out std_logic; -- vertical sync
- out_R : out std_logic_vector(9 downto 0);
- out_G : out std_logic_vector(9 downto 0);
- out_B : out std_logic_vector(9 downto 0);
- out_blank : out std_logic;
- out_sync : out std_logic;
- out_clk : out std_logic;
- in_left: in std_logic;
- in_right: in std_logic
- );
- end GAME_VGA;
- architecture DRAWING_LOGIC of GAME_VGA is
- signal last_left_state: std_logic;
- signal last_right_state: std_logic;
- signal half_clock: std_logic;
- signal one_hertz: std_logic;
- signal flip: std_logic;
- signal x: integer range 0 to 800 := 0;
- signal y: integer range 0 to 525 := 0;
- signal div: integer range 0 to 700000 := 0;
- signal offset: integer range 0 to 400 := 0;
- signal xSyncEnable: std_logic;
- signal ySyncEnable: std_logic;
- -- horizontal - x
- constant x_visibleArea : natural := 640; -- horizontal visible area
- constant x_frontPorch : natural := 16; -- horizontal front porch
- constant x_syncPulse : natural := 96; -- horizontal sync pulse
- constant x_backPorch : natural := 48; -- horizontal back porch
- constant x_total : natural := 800;
- -- vertical - y
- constant y_visibleArea : natural := 480; -- vertical visible area
- constant y_frontPorch : natural := 10; -- vertical front porch
- constant y_syncPulse : natural := 2; -- vertical sync pulse
- constant y_backPorch : natural := 33; -- vertical back porch
- constant y_total : natural := 525;
- signal color: std_logic_vector(2 downto 0) := "000";
- begin
- out_sync <= '0';
- out_blank <= '1';
- color <= "010";
- out_xSync <= xSyncEnable;
- out_ySync <= ySyncEnable;
- out_clk <= half_clock;
- -- HALFING THE CLOCK --
- clockScale: process(in_clk_50)
- begin
- if in_clk_50'event and in_clk_50 = '1' then
- half_clock <= not half_clock;
- end if;
- end process clockScale;
- -- ONE HERTZ CLOCK --
- divCounter: process(in_clk_28)
- begin
- if in_clk_28'event and in_clk_28 = '1' then
- if div = 70000 then
- div <= 0;
- one_hertz <= not one_hertz;
- else
- div <= div + 1;
- end if;
- end if;
- end process divCounter;
- -- SIGNAL TIMING --
- sig_timing: process(half_clock)
- begin
- if half_clock'event and half_clock = '1' then
- if x = x_total then
- x <= 0;
- y <= y + 1;
- if y = y_total then
- y <= 0;
- else
- y <= y + 1;
- end if;
- else
- x <= x + 1;
- end if;
- end if;
- end process sig_timing;
- offset_maker: process(one_hertz)
- begin
- if rising_edge(one_hertz) then
- if in_left = '1' and last_left_state = '0' then
- offset <= offset + 1;
- elsif in_right = '1' and last_right_state = '1' then
- offset <= offset - 1;
- end if;
- last_right_state <= in_right;
- last_left_state <= in_left;
- end if;
- end process offset_maker;
- vga_sync: process (half_clock)
- begin
- if half_clock'event and half_clock = '1' then
- if x >= (x_visibleArea + x_frontPorch) and x < (x_visibleArea + x_frontPorch + x_syncPulse) then --96 points
- xSyncEnable <= '0';
- else
- xSyncEnable <= '1';
- end if;
- if y >= (y_visibleArea + y_frontPorch) and y < (y_visibleArea + y_frontPorch + y_syncPulse) then --2 points
- ySyncEnable <= '0';
- else
- ySyncEnable <= '1';
- end if;
- end if;
- end process vga_sync;
- --
- -- draw: process(half_clock)
- -- begin
- -- if half_clock'event and half_clock = '1' then
- -- out_R(9) <= '0';
- -- out_G(9) <= '0';
- -- out_B(9) <= '0';
- --
- -- end if;
- -- end process draw;
- try_foreground: process(half_clock)
- begin
- if half_clock'event and half_clock = '1' then
- if( x >= (0 + offset) and x < (100 + offset) and y >= 200 and y < 300) and x < 640 and y < 480 then
- out_R(8) <= '1';
- out_G(8) <= '0';
- out_B(8) <= '1';
- out_R(6) <= '1';
- out_G(6) <= '0';
- out_B(6) <= '1';
- else
- out_R(8) <= '0';
- out_B(8) <= '0';
- out_R(6) <= '0';
- out_B(6) <= '0';
- end if;
- end if;
- end process try_foreground;
- end DRAWING_LOGIC;
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