library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity memoria_retencao is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           lib : in STD_LOGIC;
           btnU, btnL, btnC, btnR : in STD_LOGIC;
           sol : out STD_LOGIC;
           ad : out STD_LOGIC_VECTOR (3 downto 0));
end memoria_retencao;

architecture Behavioral of memoria_retencao is
    signal reg, buf: STD_LOGIC_VECTOR (3 downto 0);
    signal ad_sig : STD_LOGIC_VECTOR (3 downto 0);
    signal count : unsigned (1 downto 0);
    signal espera : STD_LOGIC;
begin
    armazena: process(clk, reset)
    begin
        if reset = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            for i in 3 downto 0 loop
                if buf(i) = '1' then
                    reg(i) <= '1';
                end if;
            end loop;

            if lib = '1' then
                reg <= reg and (not ad_sig); -- mascara para zerar o andar
            end if;
        end if;
    end process;
    inc: process(clk, reset)
    begin
        if reset = '1' then
            count <= "00";
        elsif rising_edge(clk) then
            if espera = '0' then
                count <= count + 1;
            end if;
        end if;
    end process;

    algoritmob: process(clk, reset)
    begin
        if reset = '1' then

        elsif rising_edge(clk) then
            if reg(to_integer(count)) = '1' then
                ad_sig(to_integer(count)) <= '1';
                ad_sig(to_integer(count)+1) <= '0';
                ad_sig(to_integer(count)+2) <= '0';
                ad_sig(to_integer(count)+3) <= '0';
                espera <= '1';
            else
                espera <= '0';
            end if;
        end if;
    end process;


end Behavioral;