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-- Company:
-- Engineer:
--
-- Create Date:    14:53:27 12/02/2019
-- Design Name:
-- Module Name:    modul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity modul is
    Port ( Y : out  STD_LOGIC;
           X : in  STD_LOGIC_VECTOR (7 downto 0);
           RST : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
              D0_RDY : in STD_LOGIC);
end modul;

architecture Behavioral of modul is

--Insert the following in the architecture before the begin keyword
   --Use descriptive names for the states, like st1_reset, st2_search
   type state_type is (q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12);
   signal state, next_state : state_type;
   --Declare internal signals for all outputs of the state-machine
   signal Y_i : std_logic;  -- example output signal
   --other outputs

begin

SYNC_PROC: process (CLK)
   begin
      if (CLK'event and CLK = '1') then
         if (RST = '1') then
            state <= q0;
         elsif (D0_RDY ='1') then
            state <= next_state;
            --<output> <= <output>_i;
         -- assign other outputs to internal signals
         end if;
      end if;
   end process;

   --MOORE State-Machine - Outputs based on state only
   OUTPUT_DECODE: process (state)
   begin
      --insert statements to decode internal output signals
      --below is simple example
      if state = q12 then
         Y <= '1';
      else
         Y <= '0';
      end if;
   end process;

   NEXT_STATE_DECODE: process (state, X)
   begin
      --declare default state for next_state to avoid latches
      next_state <= state;  --default is to stay in current state
      --insert statements to decode next_state
      --below is a simple example
      case (state) is
         when q0 =>
            if X = X"24" then
               next_state <= q1;
                else next_state <= q0;
            end if;

         when q1 =>
            if X = X"F0" then
               next_state <= q2;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q2 =>
            if X = X"24" then
               next_state <= q3;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q3 =>
            if X = X"1C" then
               next_state <= q4;
                elsif X = X"24" then
                    next_state <= q1;
                    else next_state <= q0;
            end if;

         when q4 =>
            if X = X"F0" then
               next_state <= q5;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q5 =>
            if X = X"1C" then
               next_state <= q6;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q6 =>
            if X = X"42" then
               next_state <= q7;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q7 =>
            if X = X"F0" then
               next_state <= q8;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q8 =>
            if X = X"42" then
               next_state <= q9;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q9 =>
            if X = X"44" then
               next_state <= q10;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q10 =>
            if X = X"F0" then
               next_state <= q11;
            elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q11 =>
            if X = X"44" then
               next_state <= q12;
                elsif X = X"24" then
                    next_state <= q1;
                else next_state <= q0;
            end if;

         when q12 =>
            if X = X"24" then
               next_state <= q1;
                else next_state <= q0;
            end if;

      end case;
   end process;

end Behavioral;