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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    14:53:27 12/02/2019
  6. -- Design Name:
  7. -- Module Name:    modul - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity modul is
  33.     Port ( Y : out  STD_LOGIC;
  34.            X : in  STD_LOGIC_VECTOR (7 downto 0);
  35.            RST : in  STD_LOGIC;
  36.            CLK : in  STD_LOGIC;
  37.               D0_RDY : in STD_LOGIC);
  38. end modul;
  39.  
  40. architecture Behavioral of modul is
  41.  
  42. --Insert the following in the architecture before the begin keyword
  43.    --Use descriptive names for the states, like st1_reset, st2_search
  44.    type state_type is (q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12);
  45.    signal state, next_state : state_type;
  46.    --Declare internal signals for all outputs of the state-machine
  47.    signal Y_i : std_logic;  -- example output signal
  48.    --other outputs
  49.    
  50. begin
  51.  
  52. SYNC_PROC: process (CLK)
  53.    begin
  54.       if (CLK'event and CLK = '1') then
  55.          if (RST = '1') then
  56.             state <= q0;
  57.          elsif (D0_RDY ='1') then
  58.             state <= next_state;
  59.             --<output> <= <output>_i;
  60.          -- assign other outputs to internal signals
  61.          end if;        
  62.       end if;
  63.    end process;
  64.  
  65.    --MOORE State-Machine - Outputs based on state only
  66.    OUTPUT_DECODE: process (state)
  67.    begin
  68.       --insert statements to decode internal output signals
  69.       --below is simple example
  70.       if state = q12 then
  71.          Y <= '1';
  72.       else
  73.          Y <= '0';
  74.       end if;
  75.    end process;
  76.  
  77.    NEXT_STATE_DECODE: process (state, X)
  78.    begin
  79.       --declare default state for next_state to avoid latches
  80.       next_state <= state;  --default is to stay in current state
  81.       --insert statements to decode next_state
  82.       --below is a simple example
  83.       case (state) is
  84.          when q0 =>
  85.             if X = X"24" then
  86.                next_state <= q1;
  87.                 else next_state <= q0;
  88.             end if;
  89.            
  90.          when q1 =>
  91.             if X = X"F0" then
  92.                next_state <= q2;
  93.                 elsif X = X"24" then
  94.                     next_state <= q1;
  95.                 else next_state <= q0;
  96.             end if;
  97.                
  98.          when q2 =>
  99.             if X = X"24" then
  100.                next_state <= q3;
  101.                 elsif X = X"24" then
  102.                     next_state <= q1;
  103.                 else next_state <= q0;
  104.             end if;
  105.                
  106.          when q3 =>
  107.             if X = X"1C" then
  108.                next_state <= q4;
  109.                 elsif X = X"24" then
  110.                     next_state <= q1;
  111.                     else next_state <= q0;
  112.             end if;
  113.                
  114.          when q4 =>
  115.             if X = X"F0" then
  116.                next_state <= q5;
  117.                 elsif X = X"24" then
  118.                     next_state <= q1;
  119.                 else next_state <= q0;
  120.             end if;
  121.  
  122.          when q5 =>
  123.             if X = X"1C" then
  124.                next_state <= q6;
  125.                 elsif X = X"24" then
  126.                     next_state <= q1;
  127.                 else next_state <= q0;
  128.             end if;
  129.  
  130.          when q6 =>
  131.             if X = X"42" then
  132.                next_state <= q7;
  133.                 elsif X = X"24" then
  134.                     next_state <= q1;
  135.                 else next_state <= q0;
  136.             end if;
  137.  
  138.          when q7 =>
  139.             if X = X"F0" then
  140.                next_state <= q8;
  141.                 elsif X = X"24" then
  142.                     next_state <= q1;      
  143.                 else next_state <= q0;
  144.             end if;
  145.  
  146.          when q8 =>
  147.             if X = X"42" then
  148.                next_state <= q9;
  149.                 elsif X = X"24" then
  150.                     next_state <= q1;
  151.                 else next_state <= q0;
  152.             end if;
  153.  
  154.          when q9 =>
  155.             if X = X"44" then
  156.                next_state <= q10;
  157.                 elsif X = X"24" then
  158.                     next_state <= q1;
  159.                 else next_state <= q0;
  160.             end if;
  161.  
  162.          when q10 =>
  163.             if X = X"F0" then
  164.                next_state <= q11;
  165.             elsif X = X"24" then
  166.                     next_state <= q1;
  167.                 else next_state <= q0;
  168.             end if;
  169.  
  170.          when q11 =>
  171.             if X = X"44" then
  172.                next_state <= q12;
  173.                 elsif X = X"24" then
  174.                     next_state <= q1;
  175.                 else next_state <= q0;
  176.             end if;
  177.  
  178.          when q12 =>
  179.             if X = X"24" then
  180.                next_state <= q1;
  181.                 else next_state <= q0;
  182.             end if;            
  183.  
  184.       end case;      
  185.    end process;
  186.  
  187. end Behavioral;
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