adolf01

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Apr 2nd, 2021
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity top is
  6.  
  7.     port
  8.     (
  9.             CLK         :   in  std_logic;
  10.             RESET           :   in  std_logic:='1';
  11.             RW              :   in std_logic:='1';
  12.             ADDR        :   in std_logic_vector(15 downto 0);
  13.             DATA_BUS        :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
  14.             SRAM_BA     :   BUFFER std_logic_vector(7 downto 0):="00000000";
  15.             DUART_CS        :   OUT std_logic;
  16.             VIA1_CS     :   OUT std_logic;
  17.             VIA2_CS     :   OUT std_logic;
  18.             IO_CS           :   OUT std_logic;
  19.             MEMW            :   OUT std_logic;
  20.             MEMR            :   OUT std_logic;
  21.             HRAM_CS     :   OUT std_logic;
  22.             IRQ_CS      :   OUT std_logic;
  23.             ACIA_CS     :   OUT std_logic;
  24.             RAM_CS      :   OUT std_logic;
  25.             ROM_CS      :   OUT std_logic;
  26.             AA_CS           :   OUT std_logic;
  27.             SPI_CS      :   OUT std_logic      
  28.            
  29.     );
  30.  
  31.  
  32. end entity;
  33.  
  34. architecture behavioral of top is
  35. signal CACHE    :   std_logic_vector(4 downto 0):="11111";
  36. signal decoded_address: integer range 16#0000# to 16#FFFF#;
  37. signal banks_cs : std_logic :='1';
  38.  
  39. begin
  40.  
  41. decoded_address <= to_integer(unsigned(ADDR));
  42.  
  43. SRAM_BA(4 downto 0) <= CACHE;
  44. MEMR <= NOT RW;
  45. MEMW <= RW;
  46.  
  47.  
  48.  
  49. decode_BA_RD:process (CLK)
  50. begin
  51. if rising_edge(CLK) then
  52. if RESET <= '0' then
  53.     --CACHE <= "00000000";
  54. else
  55. DATA_BUS <= "ZZZZZZZZ";
  56.    
  57.  
  58.    
  59. --if falling_edge(CLK) then
  60.     if banks_cs <= '0' then
  61.         --if RW = '0' then
  62.         --  CACHE <= DATA_BUS;
  63.         --end if;
  64.        
  65.         if RW = '1' then
  66.             DATA_BUS(4 downto 0) <= CACHE;
  67.         end if;
  68.     end if;
  69. end if;
  70. end if;
  71.  
  72. end process;
  73.  
  74. decode_BA_WR:process (CLK)
  75. begin
  76. --if falling_edge(CLK) then
  77. if RESET <= '0' then
  78.     CACHE <= "00000";
  79. end if;
  80.     if banks_cs <= '0' then
  81.         if RW = '0' then
  82.             CACHE <= DATA_BUS(4 downto 0);
  83.         end if;
  84.        
  85.     end if;
  86. --end if;
  87.  
  88.  
  89. end process;
  90.  
  91. decode:process(decoded_address)
  92. begin
  93.  
  94. ROM_CS <= '1';
  95. RAM_CS <= '1';
  96. --IO_CS <= '1';
  97. HRAM_CS <= '1';
  98.            
  99. ACIA_CS <= '1';
  100. VIA1_CS <= '1';
  101. VIA2_CS <= '1';
  102. IRQ_CS <= '1';
  103. banks_cs <= '1';
  104. DUART_CS <= '1';
  105. AA_CS  <= '1';
  106. SPI_CS  <= '1';
  107.            
  108. case decoded_address is
  109.     when 16#0000#   => banks_cs     <= '0';
  110.     when 16#0001# to 16#7FFF#   => RAM_CS       <= '0';
  111.     when 16#8000# to 16#BFFF#   => HRAM_CS      <= '0';
  112.     --when 16#C300# to 16#CEFF#     => IO_CS        <= '0';
  113.    
  114.     when 16#CF00# to 16#CF0F#   => VIA1_CS      <= '0';
  115.     when 16#CF10# to 16#CF1F#   => VIA2_CS      <= '0';
  116.     when 16#CF20# to 16#CF2F#   => IRQ_CS       <= '0';
  117.     when 16#CF30# to 16#CF3F#   => ACIA_CS      <= '0';
  118.     when 16#CF40# to 16#CF4F#   => DUART_CS         <= '0';
  119.     when 16#CF50# to 16#CF5F#   => AA_CS        <= '0';
  120.     when 16#CF60# to 16#CF6F#   => SPI_CS       <= '0';
  121.    
  122.     when 16#D000# to 16#FFFF#   => ROM_CS       <= '0';
  123.     when others => null;
  124. end case;
  125. end process;
  126.  
  127. IO_CS <= NOT(ADDR(15) AND ADDR(14) AND NOT(ADDR(13)) AND NOT(ADDR(12)));
  128.  
  129.  
  130.  
  131. end behavioral;
  132.  
  133.  
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