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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity projektASK is
- port (
- A : in signed(15 downto 0);
- B : in signed(15 downto 0);
- Salu : in signed(3 downto 0);
- LDF : in bit;
- clk : in std_logic;
- Y : out signed (15 downto 0);
- C,Z,S,P : out std_logic
- );
- end entity;
- architecture rtl of projektASK is
- begin
- process (Salu, A, B, clk)
- variable res, AA, BB,CC: signed (16 downto 0):= (others => '0');
- variable CF,ZF,SF,PF : std_logic:= '0';
- variable temp: signed (7 downto 0):= (others => '0');
- begin
- AA(16) := A(15);
- AA(15 downto 0) := A;
- BB(16) := B(15);
- BB(15 downto 0) := B;
- CC(0) := CF;
- CC(16 downto 1) := "0000000000000000";
- case Salu is
- when "0000" => res := AA;
- when "0001" => res := AA + BB;
- when "0010" => res := AA - BB;
- when "0011" => if(AA = BB) then AA := res;
- BB := res;
- end if;
- when "0100" => if(AA >= BB) then AA := res;
- BB := res;
- end if;
- when "0101" => if(AA > BB) then res :="00000000000000001";
- else res := "00000000000000000";
- end if;
- when "0110" => if(AA <= BB) then res :="00000000000000001";
- else res := "00000000000000000";
- end if;
- when "0111" => if(AA < BB) then res :="00000000000000001";
- else res := "00000000000000000";
- end if;
- when "1000" => AA := AA xor BB; -- or;
- when "1001" => AA := shift_left(signed(AA), to_integer(signed(BB)));
- when "1010" => AA := shift_right(signed(AA), to_integer(signed(BB)));
- when OTHERS => res(16) := AA(16);
- --res(15 downto 0) := AA(16 downto 1);
- res(15 downto 0) := AA(15 downto 0);
- end case;
- Y <= res(15 downto 0);
- Z <= ZF;
- S <= SF;
- C <= CF;
- P <= PF;
- if (clk'event and clk='1') then
- if (LDF='1') then
- if (res = "00000000000000000") then
- ZF:='1';
- else ZF:='0';
- end if;
- if (res(15)='1') then SF:='1';
- else SF:='0'; end if;
- CF := res(16) xor res(15);
- end if;
- end if;
- end process;
- end rtl;
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