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- --- CONTROL START ---
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- Entity Control is
- port(
- op : in std_logic_vector( 3 downto 0);
- alu_op : out std_logic_vector( 1 downto 0);
- alu_src : out std_logic;
- reg_dest : out std_logic;
- reg_load : out std_logic;
- reg_src : out std_logic_vector(1 downto 0);
- mem_read : out std_logic;
- mem_write : out std_logic
- );
- End Control;
- architecture syn of Control is
- begin
- process (op) is
- begin
- case op is
- -- op=0, ADD
- when x"0" =>
- alu_op <= "00";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=1, SUB
- when x"1" =>
- alu_op <= "01";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=2, AND
- when x"2" =>
- alu_op <= "10";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=3, OR
- when x"3" =>
- alu_op <= "11";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=4, ADDi
- when x"4" =>
- alu_op <= "00";
- alu_src <= '1';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=5, SUBi
- when x"5" =>
- alu_op <= "01";
- alu_src <= '1';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '0';
- -- op=8, LW
- when x"8" =>
- alu_op <= "00";
- alu_src <= '1';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "00";
- mem_read <= '1';
- mem_write <= '0';
- -- op=C, SW
- when x"C" =>
- alu_op <= "00";
- alu_src <= '1';
- reg_dest <= '1';
- reg_load <= '0';
- reg_src <= "01";
- mem_read <= '0';
- mem_write <= '1';
- -- op=7, SLT
- when x"7" =>
- alu_op <= "01";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '1';
- reg_src <= "11";
- mem_read <= '0';
- mem_write <= '0';
- when others =>
- alu_op <= "00";
- alu_src <= '0';
- reg_dest <= '0';
- reg_load <= '0';
- reg_src <= "01";
- mem_read <= '0';
- mem_write<= '0';
- end case;
- end process;
- end syn;
- --- CONTROL END ---
- --- CPU_2214 START ---
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
- entity CPU_2214 is
- port(
- clk : in std_logic;
- clear : in std_logic;
- mem_dump : in std_logic := '0';
- instruction : in std_logic_vector(15 downto 0)
- );
- end CPU_2214;
- architecture Behavioral of CPU_2214 is
- COMPONENT ALU_16Bit
- port(
- A : in std_logic_vector(15 downto 0);
- B : in std_logic_vector(15 downto 0);
- S : in std_logic_vector(1 downto 0);
- Sout : out std_logic_vector(15 downto 0);
- Cout : out std_logic
- );
- END COMPONENT;
- COMPONENT Registers
- port(
- clk : in std_logic;
- clear : in std_logic;
- a_addr : in std_logic_vector( 3 downto 0);
- a_data : in std_logic_vector(15 downto 0);
- load : in std_logic;
- b_addr : in std_logic_vector( 3 downto 0);
- c_addr : in std_logic_vector( 3 downto 0);
- b_data : out std_logic_vector(15 downto 0);
- c_data : out std_logic_vector(15 downto 0)
- );
- END COMPONENT;
- COMPONENT Control
- port(
- op : in std_logic_vector( 3 downto 0);
- alu_op : out std_logic_vector( 1 downto 0);
- alu_src : out std_logic;
- reg_dest : out std_logic;
- reg_load : out std_logic;
- reg_src : out std_logic_vector( 1 downto 0);
- mem_read : out std_logic;
- mem_write : out std_logic
- );
- end component;
- component Signextend
- port(
- immIn : in std_logic_vector( 3 downto 0);
- immOut : out std_logic_vector(15 downto 0)
- );
- end component;
- component mux3_1
- generic (WIDTH : positive:=16);
- port(
- Input1 : in std_logic_vector(WIDTH-1 downto 0);
- Input2 : in std_logic_vector(WIDTH-1 downto 0);
- Input3 : in std_logic_vector(WIDTH-1 downto 0);
- S : in std_logic_vector(1 downto 0);
- Sout : out std_logic_vector(WIDTH-1 downto 0));
- end component;
- component mux2_1
- generic (WIDTH : positive:=16);
- port(
- Input1 : in std_logic_vector(WIDTH-1 downto 0);
- Input2 : in std_logic_vector(WIDTH-1 downto 0);
- S : in std_logic;
- Sout : out std_logic_vector(WIDTH-1 downto 0));
- end component;
- component Memory
- generic (
- INPUT : string := "in.txt";
- OUTPUT : string := "out.txt"
- );
- port (
- clk : in std_logic;
- read_en : in std_logic;
- write_en : in std_logic;
- addr : in std_logic_vector(15 downto 0);
- data_in : in std_logic_vector(15 downto 0);
- data_out : out std_logic_vector(15 downto 0);
- mem_dump : in std_logic := '0'
- );
- end component;
- -- Signals
- signal op : std_logic_vector( 3 downto 0) ;
- signal rd : std_logic_vector( 3 downto 0) ;
- signal rs : std_logic_vector( 3 downto 0) ;
- signal rt : std_logic_vector( 3 downto 0) ;
- signal alu_result : std_logic_vector(15 downto 0);
- signal alu_src_mux_out : std_logic_vector(15 downto 0);
- signal sign_ex_out : std_logic_vector(15 downto 0);
- signal rs_data : std_logic_vector(15 downto 0);
- signal rt_data : std_logic_vector(15 downto 0);
- signal reg_dest_mux_out : std_logic_vector( 3 downto 0);
- signal reg_src_mux_out : std_logic_vector(15 downto 0);
- signal mem_dataout : std_logic_vector(15 downto 0);
- signal ctrl_alu_src : std_logic;
- signal ctrl_alu_op : std_logic_vector( 1 downto 0);
- signal ctrl_reg_dest : std_logic;
- signal ctrl_reg_src : std_logic_vector( 1 downto 0);
- signal ctrl_reg_load : std_logic;
- signal ctrl_mem_read : std_logic;
- signal ctrl_mem_write : std_logic;
- signal slt_input : std_logic_vector(15 downto 0);
- begin
- --------------------------------------------------------------------------
- -- Instruction Fetch
- --------------------------------------------------------------------------
- op <= instruction(15 downto 12);
- rd <= instruction(11 downto 8);
- rs <= instruction(7 downto 4);
- rt <= instruction(3 downto 0);
- --------------------------------------------------------------------------
- -- Instruction Decode
- --------------------------------------------------------------------------
- CPU_Control_0: Control port map(
- op => op,
- alu_op => ctrl_alu_op,
- alu_src => ctrl_alu_src,
- reg_dest => ctrl_reg_dest,
- reg_load => ctrl_reg_load,
- reg_src => ctrl_reg_src,
- mem_read => ctrl_mem_read,
- mem_write => ctrl_mem_write
- );
- CPU_Registers_0: Registers port map(
- clk => clk,
- clear => clear,
- a_addr => rd,
- a_data => reg_src_mux_out,
- load => ctrl_reg_load,
- b_addr => rs,
- c_addr => reg_dest_mux_out,
- b_data => rs_data,
- c_data => rt_data
- );
- CPU_signextend_0: Signextend port map(
- immIn => rt,
- immOut => sign_ex_out
- );
- CPU_reg_dest_mux: mux2_1 generic map(4) port map(
- Input1 => rt,
- Input2 => rd,
- S => ctrl_reg_dest,
- Sout => reg_dest_mux_out
- );
- --------------------------------------------------------------------------
- -- Execute
- --------------------------------------------------------------------------
- CPU_alu_src_mux: mux2_1 generic map(16) port map(
- Input1 => rt_data,
- Input2 => sign_ex_out,
- S => ctrl_alu_src,
- Sout => alu_src_mux_out
- );
- CPU_ALU_0: ALU_16Bit port map(
- A => rs_data,
- B => alu_src_mux_out,
- S => ctrl_alu_op,
- Sout => alu_result,
- Cout => open
- );
- --------------------------------------------------------------------------
- -- Memory
- --------------------------------------------------------------------------
- CPU_MEM_0:Memory port map(
- clk => clk,
- read_en => ctrl_mem_read,
- write_en => ctrl_mem_write,
- addr => alu_result,
- data_in => rt_data,
- data_out => mem_dataout,
- mem_dump => '0'
- );
- --------------------------------------------------------------------------
- -- Write Back alu_result and
- --------------------------------------------------------------------------
- slt_input <= "000000000000000"&(alu_result(15));
- CPU_reg_src_mux: mux3_1 generic map(16) port map(
- Input1 => mem_dataout,
- Input2 => alu_result,
- Input3 => slt_input,
- S => ctrl_reg_src,
- Sout => reg_src_mux_out
- );
- end Behavioral;
- --- CPU_2214 END ---
- --- CPU_2214_TB START ---
- library ieee;
- use ieee.std_logic_1164.all;
- entity CPU_2214_Test is
- end entity CPU_2214_Test;
- architecture mixed of CPU_2214_Test is
- constant tick : time := 100 ns;
- signal reset, clock : std_logic;
- signal mem_dump : std_logic := '0';
- signal instruction : std_logic_vector(0 to 15);
- begin
- uut : entity work.CPU_2214
- port map(
- clk => clock,
- clear => reset,
- instruction => instruction,
- mem_dump => mem_dump
- );
- driver : process is
- begin
- -- reset the system
- reset <= '0'; instruction <= x"0000"; wait for 50 ns;
- reset <= '1';
- -- ADDI r3, r0, 5 (r3 = 5)
- instruction <= x"4305"; wait for tick;
- -- ADDI r4, r0, 2 (r4 = 2)
- instruction <= x"4402"; wait for tick;
- -- SLT r11,r3, r4 (r11 = 0)
- instruction <= x"7B34"; wait for tick;
- -- SW r3, 0(r0) (M[0] = 5)
- instruction <= x"C300"; wait for tick;
- -- SW r4, 4(r0) (M[4] = 2)
- instruction <= x"C404"; wait for tick;
- -- ADDI r6, r0, 4 (r6 = 4)
- instruction <= x"4604"; wait for tick;
- -- LW r7, 0(r6) (r7 = 2)
- instruction <= x"8760"; wait for tick;
- -- LW r8, 0(r0) (r8 = 5)
- instruction <= x"8800"; wait for tick;
- -- ADD r9,r7,r8 (r9 = 7)
- instruction <= x"0978"; wait for tick;
- -- SLT r10,r0,r1 (r10 = 1)
- instruction <= x"7A01"; wait for tick;
- -- SLT r10,r1,r0 (r10 = 0)
- instruction <= x"7A10"; wait for tick;
- wait;
- end process driver;
- clock_p : process is
- begin
- for i in 0 to 100 loop
- clock <= '1'; wait for tick/2;
- clock <= '0'; wait for tick/2;
- end loop;
- wait;
- end process clock_p;
- end architecture mixed;
- --- CPU_2214_TB END ---
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