LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


entity MULTI_2_TO_1 is
    port (SEL, A, B: in std_logic;
    Y: out std_logic);
end MULTI_2_TO_1;

architecture DESCRIPTION of MULTI_2_TO_1 is
begin
    Y <= ((SEL and A) or (not (SEL) and B));
end DESCRIPTION;