[PSDS] Dec.Counter from 0 to 9

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity dec_counter is
    Port ( en : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk : in STD_LOGIC;
           pulse : out STD_LOGIC;
           q : out STD_LOGIC_VECTOR (3 downto 0));
end dec_counter;

architecture Behavioral of dec_counter is
  signal count:std_logic_vector(3 downto 0);
  signal pulse_s:std_logic;
begin
  process(clk) is
  begin
    if(clk='1' and clk'event) then
      if(reset='1') then
        count<="0000";
        pulse_s<='0';
      elsif(en='1') then
        if(count<"1001") then
          count<=count+1;
        else
          count<="0000";
        end if;
      end if;
    end if;
  end process;

  q<=count;
  pulse<='1' when count="1001" and en='1' else '0';

end Behavioral;