TOP_LEVEL kaskadna direktna FIR NE RADI!!!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.util_pkg.all;

entity TOP_LEVEL is
    generic(fir_ord : natural := 10;
            input_data_width : natural := 12;
            output_data_width : natural := 12);
    Port ( clk_i : in STD_LOGIC;
           ce_i : in STD_LOGIC;
           coef_addr_i1 : in STD_LOGIC_VECTOR (log2c(fir_ord+1)-1 downto 0);
           coef_addr_i2 : in STD_LOGIC_VECTOR (log2c(fir_ord+1)-1 downto 0);
           coef_addr_i3 : in STD_LOGIC_VECTOR (log2c(fir_ord+1)-1 downto 0);
           coef_i1 : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           coef_i2 : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           coef_i3 : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           we_i : in STD_LOGIC;
           data_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           data_o : out STD_LOGIC_VECTOR (output_data_width-1 downto 0));
end TOP_LEVEL;

architecture Behavioral of TOP_LEVEL is
    type std_2d is array (fir_ord downto 0) of
        std_logic_vector(2*input_data_width-1 downto 0);
    signal mac_inter : std_2d:=(others=>(others=>'0'));

    type coef_t is array (fir_ord downto 0) of
            std_logic_vector(input_data_width-1 downto 0);
    signal b_s1 : coef_t := (others=>(others=>'0'));
    signal b_s2 : coef_t := (others=>(others=>'0'));
    signal b_s3 : coef_t := (others=>(others=>'0'));
begin
    process(clk_i)
    begin
        if(clk_i'event and clk_i = '1')then
            if (ce_i = '1' and we_i = '1') then
                b_s1(to_integer(unsigned(coef_addr_i1))) <= coef_i1;
                b_s2(to_integer(unsigned(coef_addr_i2))) <= coef_i2;
                b_s3(to_integer(unsigned(coef_addr_i3))) <= coef_i3;
            end if;
        end if;
    end process;
    first_section:
        entity work.ASK(behavioral)
        generic map(input_data_width=>input_data_width)
        port map(clk_i=>clk_i,
                 ce_i=>ce_i,
                 u_i=>data_i,
                 b_i=>b_s1(0),
                 b_j=>b_s2(0),
                 b_k=>b_s3(0),
                 o_i=>mac_inter(0));
     other_sections:
        for i in 1 to fir_ord generate
        fir_section:
        entity work.ASK(behavioral)
        generic map(input_data_width=>input_data_width)
        port map(clk_i=>clk_i,
                 ce_i=>ce_i,
                 u_i=>mac_inter(i-1),
                 b_i=>b_s1(i),
                 b_j=>b_s2(i),
                 b_k=>b_s3(i),
                 o_i=>mac_inter(i));
        end generate;

       process(clk_i)
            begin
               if(clk_i'event and clk_i='1')then
                   if (ce_i = '1') then
                       data_o <= mac_inter(fir_ord)
                           (2*input_data_width-2 downto 2*input_data_width-output_data_width-1);
                   end if;
               end if;
           end process;

end Behavioral;