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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 20:11:46 05/22/2019
- -- Design Name:
- -- Module Name: rs232 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- ---- Uncomment the following library declaration if instantiating
- ---- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity rs232 is
- Port ( clk_i : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- RXD_i : in STD_LOGIC;
- led : out STD_LOGIC_VECTOR(7 downto 0);
- TXD_o : out STD_LOGIC := '1');
- end rs232;
- architecture Behavioral of rs232 is
- signal data : STD_LOGIC_VECTOR(7 downto 0):=(others => '0');
- signal flipflop: std_logic := '1';
- signal slopping_edge: std_logic := '0';
- signal RXD_now: std_logic;
- signal RXD_before: std_logic;
- signal data_receiving: std_logic := '0';
- signal data_sending: std_logic := '0';
- --signal RXD_index: integer := 0;
- begin
- led <= data;
- receiver: process(clk_i, rst_i)
- variable counter : integer := 0;
- variable RXD_index : integer := 0;
- begin
- if rst_i = '1' then
- flipflop <= '1';
- RXD_now <= '1';
- RXD_before <= '1';
- slopping_edge <= '0';
- counter := 0;
- RXD_index := 0;
- data_receiving <= '0';
- data <= (others => '0');
- elsif rising_edge(clk_i) then
- flipflop <= RXD_i;
- RXD_now <= flipflop;
- if RXD_now = '0' and RXD_before = '1' and data_receiving = '0' then
- slopping_edge <= '1'; --opadajace
- end if;
- if slopping_edge = '1' then
- if counter = 2604 and RXD_now = '0' then
- data_receiving <= '1';
- counter := -1;
- end if;
- counter := counter + 1;
- end if;
- if data_receiving = '1' then
- slopping_edge <= '0';
- if counter = 5208 then
- data(RXD_index) <= RXD_now;
- RXD_index := RXD_index + 1;
- counter := -1;
- if RXD_index = 8 then
- RXD_index := 0;
- data_receiving <= '0';
- end if;
- end if;
- counter := counter + 1;
- end if;
- RXD_before <= RXD_now;
- end if;
- end process;
- transmiter: process(clk_i, rst_i)
- variable counter : integer := 0;
- variable TXD_index : integer := 0;
- begin
- if rst_i = '1' then
- data_sending <= '0';
- counter := 0;
- TXD_index := 0;
- TXD_o <= '1';
- elsif(rising_edge(clk_i)) then
- if(data_receiving = '0' and data /= "00000000") then
- if(data_sending = '0') then
- TXD_o <= '0';
- data_sending <= '1';
- --counter := 0;
- else
- TXD_o <= '1';
- end if;
- end if;
- if(data_sending = '1' and counter = 5208) then
- if counter = 5208 then
- if TXD_index = 8 then
- TXD_index := 0;
- TXD_o <= '1';
- data_sending <= '0';
- else
- TXD_o <= data(TXD_index);
- TXD_index := TXD_index + 1;
- end if;
- counter := 0;
- else counter := counter +1;
- end if;
- end if;
- end if;
- -- if(data_receiving = '0') then
- -- case TXD_index is
- -- when 0 => TXD_o <= '0';
- -- TXD_index := TXD_index + 1;
- -- when 1 to 8 => if counter = 5208 then TXD_o <= data(TXD_index-1);
- -- TXD_index := TXD_index + 1;
- -- end if;
- -- when others => if counter = 5208 then TXD_o <= '1';
- -- counter := -1;
- -- TXD_index := 0;
- -- end if;
- -- end case;
- -- counter := counter + 1;
- -- end if;
- --
- -- if(data_receiving = '0') then
- -- if TXD_index = 0 then
- -- TXD_o <= '0';
- -- TXD_index := 1;
- -- --start <= '1';
- -- elsif TXD_index 1 to 8 then
- -- if(counter = 5208) then
- -- TXD_o <= data(TXD_index);
- -- counter := 0;
- -- else
- -- counter := counter + 1;
- -- end if;
- -- else
- -- TXD_o <= '1';
- -- end if;
- -- else
- -- TXD_o <= '1';
- -- end if;
- end process;
- end Behavioral;
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