vhdl

entity project1 is
    port (x1, x2, x3, x4, clkin, xx1 : in bit;
          k1, k2, k3 : in bit_vector (7 downto 0);
          y1, y2, y3, y4, yy2, yy3, y10 : out bit);
end project1;

architecture project1_arch of project1 is

    component SCH
    port (a: in bit;
          b: out bit_vector (2 downto 0));
    end component;

    component comp
    port (a: in bit_vector (2 downto 0);
          i_clkin: in bit;
          b, i_clkout: out bit);
    end component;

    component pass
        port (k1, k2, k3: in bit_vector (7 downto 0);
              clkin: in bit;
              y10: out bit);
    end component;

        component EX2
        port(A,B : in bit;
             Y : out bit);
        end component;

        component N
        port (A : in bit;
              Y : out bit);
        end component;

        component NO3A2
        port (A,B,C,D : in bit;
              Y : out bit);
        end component;

        component NA2
        port (A,B : in bit;
              Y : out bit);
        end component;

        component NA3O2
        port (A,B,C,D : in bit;
              Y : out bit);
        end component;

        component NOA3
        port (A,B,C,D : in bit;
              Y : out bit);
        end component;

        component VCC
        port (Y : out bit);
        end component;

        component NO3
        port (A,B,C : in bit;
              Y : out bit);
        end component;

        component NOAO2
        port (A,B,C,D : in bit;
              Y : out bit);
        end component;

        component NAO2
        port (A,B,C : in bit;
              Y : out bit);
        end component;


    signal s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15 : bit;
    signal ss1 : bit_vector (2 downto 0);

    begin

    SCH1 : SCH port map (xx1, ss1);
    comp1 : comp port map (ss1, xx1, yy2, yy3);
    pass1: pass port map (k1, k2, k3, clkin, y10);


    EX2_1: EX2 port map(x3,x2,s0);
    N_1: N port map(s0,s1);
    N_2: N port map(s14,s2);
    N_3: N port map(s2,s3);
    N_4: N port map(s1,s4);
    N_5: N port map(x1,s5);
    NO3A2_1: NO3A2 port map(x4,s3,s4,s5,s6);
    N_6: N port map(x4,s7);
    N_7: N port map(x2,s8);
    N_8: N port map(s1,s9);
    NA2_1: NA2 port map(s5,x4,s10);
    NA3O2_1: NA3O2 port map(x3,s2,x1,s7,s11);
    NOA3_1: NOA3 port map(s6,x3,s8,x1,s12);
    N_9: N port map(s15,s13);
    VCC_1: VCC port map(y1);
    NO3_1: NO3 port map(s9,x4,s5,s14);
    NOAO2_1: NOAO2 port map(s8,s11,x3,s10,s15);
    NAO2_1: NAO2 port map(s12,x1,s13,y4);
y2<=s14;
y3<=s15;

end project1_arch;



entity EX2 is
port(A,B : in bit;
     Y : out bit);
end EX2;

architecture EX2_arch of EX2 is
begin
    y <= ((A and (not B)) or ((not A) and B)) after 5 ns;
end EX2_arch;

entity N is
port (A : in bit;
      Y : out bit);
end N;

architecture N_arch of N is
begin
    y <= (not A) after 1 ns;
end N_arch;

entity NO3A2 is
port (A,B,C,D : in bit;
      Y : out bit);
end NO3A2;

architecture NO3A2_arch of NO3A2 is
begin
    y <= not(A or B or (D and C)) after 5 ns;
end NO3A2_arch;

entity NA2 is
port (A,B : in bit;
      Y : out bit);
end NA2;

architecture NA2_arch of NA2 is
begin
    y <= not(A and B) after 2 ns;
end NA2_arch;

entity NA3O2 is
port (A,B,C,D : in bit;
      Y : out bit);
end NA3O2;

architecture NA3O2_arch of NA3O2 is
begin
    y <= not(A and B and (C or D)) after 4 ns;
end NA3O2_arch;

entity NOA3 is
port (A,B,C,D : in bit;
      Y : out bit);
end NOA3;

architecture NOA3_arch of NOA3 is
begin
    y <= not(A or (B and C and D)) after 5 ns;
end NOA3_arch;

entity VCC is
port (Y : out bit);
end VCC;

architecture VCC_arch of VCC is
begin
    y <= '1' after 1 ns;
end VCC_arch;

entity NO3 is
port (A,B,C : in bit;
      Y : out bit);
end NO3;

architecture NO3_arch of NO3 is
begin
    y <= not(A or B or C) after 4 ns;
end NO3_arch;

entity NOAO2 is
port (A,B,C,D : in bit;
      Y : out bit);
end NOAO2;

architecture NOAO2_arch of NOAO2 is
begin
    y <= not(A or (B and (C or D))) after 4 ns;
end NOAO2_arch;

entity NAO2 is
port (A,B,C : in bit;
      Y : out bit);
end NAO2;

architecture NAO2_arch of NAO2 is
begin
    y <= not(A and (B or C)) after 3 ns;
end NAO2_arch;

entity SCH is
    port (a: in bit;
          b: out bit_vector (2 downto 0));
end SCH;

    architecture SCH_arch of SCH is
        begin
        process(a)
        variable sum1: integer := 0;
        begin
            if ((a'event) and (a = '1')) then
                sum1 := sum1 + 1;
                if (sum1 = 8) then
                    sum1 := 0;
                end if;
                case sum1 is
                    when 0 => b <= "000";
                    when 1 => b <= "001";
                    when 2 => b <= "010";
                    when 3 => b <= "011";
                    when 4 => b <= "100";
                    when 5 => b <= "101";
                    when 6 => b <= "110";
                    when 7 => b <= "111";
                    when others =>
                end case;
            end if;
        end process;
    end  SCH_arch;

    entity comp is
    port (a: in bit_vector (2 downto 0);
          i_clkin: in bit;
          b, i_clkout: out bit);
    end comp;

    architecture comp_arch of comp is
    begin
        process(a)
        variable sum2 : integer := 0;
        begin
            i_clkout <= '1', '0' after 20 ns;
            if (a = "100") then
            sum2 := sum2 + 1;
            if (sum2 = 1) then
            i_clkout <= '0', '1' after 20 ns;
            else i_clkout <= '1', '0' after 20 ns;
            end if;
            if (sum2 = 1) then
            b <= '1', '0' after 20 ns;
            end if;
            end if;

        end process;

    end  comp_arch;

    entity pass is
    port (k1, k2, k3: in bit_vector (7 downto 0);
          clkin: in bit;
          y10: out bit);
    end pass;

    architecture pass_arch of pass is

        begin
        process(clkin)
        variable ntakta : integer := 0;
        variable ok1 : integer := 0;
        begin
        ntakta := ntakta + 1;
        ok1 := 0;
        if ((ntakta = 1) and (k1 = "01010101") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 2) and (k2 = "11001100") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 3) and (k3 = "11001100") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 4) and (k3 = "11001100") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 5) and (k1 = "01010101") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 6) and (k3 = "01010101") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 7) and (k3 = "01010101") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;
        if ((ntakta = 8) and (k2 = "01010101") and (clkin'event) and (clkin = '1'))
        then ok1 := 1;
        end if;

        if (ok1 = 0) then ntakta := 0;
        end if;
        if ((ntakta = 8) and (clkin'event) and (clkin = '1'))
        then y10 <= '1', '0' after 20 ns;
        ntakta := 0;
        end if;
        end process;

    end pass_arch;