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- bramka_or:
- library ieee;
- use ieee.std_logic_1164.all;
- entity bramka_or is
- port( x1_or, x2_or: in bit;
- out_or: out bit);
- end bramka_or;
- architecture struct of bramka_or is
- begin
- out_or <= x1_or or x2_or;
- end struct;
- ////////////////////////////////////////////////////////////////////////
- bramka_and:
- library ieee;
- use ieee.std_logic_1164.all;
- entity bramka_and is
- port( x1_and, x2_and: in bit;
- out_and: out bit);
- end bramka_and;
- architecture struct of bramka_and is
- begin
- out_and <= x1_and and x2_and;
- end struct;
- ////////////////////////////////////////////////////////////////////////
- andor:
- library ieee;
- use ieee.std_logic_1164.all;
- entity andor is
- port( x1_andor, x2_andor, x3_andor: in bit;
- out_andor: out bit);
- end andor;
- architecture struct of andor is
- component bramka_and is
- port( x1_and, x2_and: in bit;
- out_and: out bit);
- end component;
- component bramka_or is
- port( x1_or, x2_or: in bit;
- out_or: out bit);
- end component;
- signal and_result: bit;
- begin
- Gate1: bramka_and port map (x1_and=>x1_andor, x2_and=>x2_andor, out_and=>and_result);
- Gate2: bramka_or port map (x1_or=>and_result, x2_or=>x3_andor, out_or=>out_andor);
- end struct;
- ////////////////////////////////////////////////////////////////////////
- top_module:
- library ieee;
- use ieee.std_logic_1164.all;
- entity top_module is
- port( x1_top, x2_top, x3_top, x4_top: in bit;
- out_top: out bit);
- end top_module;
- architecture struct of top_module is
- component bramka_and is
- port( x1_and, x2_and: in bit;
- out_and: out bit);
- end component;
- component andor is
- port( x1_andor, x2_andor, x3_andor: in bit;
- out_andor: out bit);
- end component;
- signal out_andor1, out_andor2: bit;
- begin
- M1: andor port map (x1_top, x2_top, x3_top, out_andor1);
- M2: andor port map (x2_top, x4_top, x1_top, out_andor2);
- Gate1: bramka_and port map (out_andor1, out_andor2, out_top);
- end struct;
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