majczel23000

[ASK] top_module

Mar 14th, 2018
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VHDL 1.93 KB | None | 0 0
  1. bramka_or:
  2.  
  3. library ieee;
  4. use ieee.std_logic_1164.all;
  5. entity bramka_or is
  6.     port( x1_or, x2_or: in bit;
  7.             out_or: out bit);
  8. end bramka_or;
  9. architecture struct of bramka_or is
  10. begin
  11.     out_or <= x1_or or x2_or;
  12. end struct;
  13.  
  14. ////////////////////////////////////////////////////////////////////////
  15.  
  16. bramka_and:
  17.  
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. entity bramka_and is
  21.     port( x1_and, x2_and: in bit;
  22.             out_and: out bit);
  23. end bramka_and;
  24. architecture struct of bramka_and is
  25. begin
  26.     out_and <= x1_and and x2_and;
  27. end struct;
  28.  
  29. ////////////////////////////////////////////////////////////////////////
  30.  
  31. andor:
  32.  
  33. library ieee;
  34. use ieee.std_logic_1164.all;
  35. entity andor is
  36.     port( x1_andor, x2_andor, x3_andor: in bit;
  37.             out_andor: out bit);
  38. end andor;
  39. architecture struct of andor is
  40.     component bramka_and is
  41.         port( x1_and, x2_and: in bit;
  42.                 out_and: out bit);
  43.     end component;
  44.     component bramka_or is
  45.         port( x1_or, x2_or: in bit;
  46.                 out_or: out bit);
  47.     end component;
  48.     signal and_result: bit;
  49. begin
  50.     Gate1: bramka_and port map (x1_and=>x1_andor, x2_and=>x2_andor, out_and=>and_result);
  51.     Gate2: bramka_or port map (x1_or=>and_result, x2_or=>x3_andor, out_or=>out_andor);  
  52. end struct;
  53.  
  54.  
  55. ////////////////////////////////////////////////////////////////////////
  56.  
  57. top_module:
  58.  
  59. library ieee;
  60. use ieee.std_logic_1164.all;
  61. entity top_module is
  62.     port( x1_top, x2_top, x3_top, x4_top: in bit;
  63.             out_top: out bit);
  64. end top_module;
  65. architecture struct of top_module is
  66.     component bramka_and is
  67.         port( x1_and, x2_and: in bit;
  68.                 out_and: out bit);
  69.     end component;
  70.     component andor is
  71.         port( x1_andor, x2_andor, x3_andor: in bit;
  72.                 out_andor: out bit);
  73.     end component;
  74.     signal out_andor1, out_andor2: bit;
  75. begin
  76.     M1: andor port map (x1_top, x2_top, x3_top, out_andor1);
  77.     M2: andor port map (x2_top, x4_top, x1_top, out_andor2);
  78.     Gate1: bramka_and port map (out_andor1, out_andor2, out_top);
  79. end struct;
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