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- library ieee;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.numeric_std.all;
- entity vend is
- port (
- rstb : in std_logic;
- clk : in std_logic;
- sw : in std_logic_vector(9 downto 0);
- led : out std_logic_vector(4 downto 0);
- seg1 : out std_logic_vector(7 downto 0);
- seg2 : out std_logic_vector(7 downto 0);
- seg3 : out std_logic_vector(7 downto 0);
- seg4 : out std_logic_vector(7 downto 0);
- seg5 : out std_logic_vector(7 downto 0);
- seg6 : out std_logic_vector(7 downto 0);
- --Ds : out std_logic_vector(5 downto 0);
- choose : out std_logic_vector(4 downto 0)
- );
- end entity;
- architecture behavioral of vend is
- type state_type is (rdy,vend,err,cancel);--states
- signal state : state_type;
- signal state_next : state_type;
- signal cnt: unsigned(10 downto 0);
- signal delay: unsigned(10 downto 0);
- signal clk1hz : std_logic;
- signal clockcnt : integer range 0 to 25000000;
- signal As : unsigned(5 downto 0); --quarters
- signal Bs : unsigned(5 downto 0); --nickles
- signal Cs : unsigned(5 downto 0); --dimes
- signal Ds : unsigned(5 downto 0); --total
- constant a : std_logic_vector(7 downto 0) := "10001000";
- constant b : std_logic_vector(7 downto 0) := "10000011";
- constant C : std_logic_vector(7 downto 0) := "10100111";
- constant d : std_logic_vector(7 downto 0) := "10100101";
- constant E : std_logic_vector(7 downto 0) := "10000110";
- constant F : std_logic_vector(7 downto 0) := "10001110";
- constant G : std_logic_vector(7 downto 0) := "11000010";
- constant H : std_logic_vector(7 downto 0) := "10001001";
- constant i : std_logic_vector(7 downto 0) := "11101111";
- constant j : std_logic_vector(7 downto 0) := "11100001";
- --NO k
- constant L : std_logic_vector(7 downto 0) := "10000111";
- --NO m
- constant n : std_logic_vector(7 downto 0) := "10101011";
- constant o : std_logic_vector(7 downto 0) := "10100011";
- constant P : std_logic_vector(7 downto 0) := "10001100";
- constant q : std_logic_vector(7 downto 0) := "10110000";
- constant r : std_logic_vector(7 downto 0) := "10101111";
- constant s : std_logic_vector(7 downto 0) := "10010011";
- constant t : std_logic_vector(7 downto 0) := "10000111";
- constant U : std_logic_vector(7 downto 0) := "11000001";
- --NO v
- constant w : std_logic_vector(7 downto 0) := "10000001";
- --NO x
- constant y : std_logic_vector(7 downto 0) := "10010001";
- --NO z
- constant s0 : std_logic_vector(7 downto 0) := "11000000";
- constant s1 : std_logic_vector(7 downto 0) := "11111001";
- constant s2 : std_logic_vector(7 downto 0) := "10100100";
- constant s3 : std_logic_vector(7 downto 0) := "10110000";
- constant s4 : std_logic_vector(7 downto 0) := "10011001";
- constant s5 : std_logic_vector(7 downto 0) := "10010010";
- constant s6 : std_logic_vector(7 downto 0) := "10000010";
- constant s7 : std_logic_vector(7 downto 0) := "11111000";
- constant s8 : std_logic_vector(7 downto 0) := "10000000";
- constant s9 : std_logic_vector(7 downto 0) := "10010000"; --fill this in later
- constant blank : std_logic_vector(7 downto 0):="11111111";
- constant dash: std_logic_vector (7 downto 0):="00001000";
- --state machine --rdy,chip,candy,vend,err
- begin
- process(all)
- begin
- case state is
- when rdy =>
- if(sw(0) = '1')then--chip1
- choose(0)<='1';
- if(Ds >= "110010")then
- state_next<=vend;
- else
- state_next<=rdy;
- end if;
- elsif(sw(1) = '1')then--chip2
- choose(1)<='1';
- if(Ds >= "110010")then
- state_next<=vend;
- else
- state_next<=rdy;
- end if;
- elsif(sw(2) = '1')then--candy1
- choose(2)<='1';
- if(Ds >= "111100")then
- state_next<=vend;
- else
- state_next<=rdy;
- end if;
- elsif(sw(3) = '1')then--candy2
- choose(3)<='1';
- if(Ds >= "111100")then
- state_next<=vend;
- else
- state_next<=rdy;
- end if;
- elsif(sw(4) = '1')then--candy3
- choose(4)<='1';
- if(Ds >= "111100")then
- state_next<=vend;
- else
- state_next<=rdy;
- end if;
- elsif(sw(5) = '1')then--cancel
- state_next<=cancel;
- elsif(sw(6) = '1')then--quarters
- --As<= "011001";
- Ds<= Ds + B"011001";
- --Ds<=std_logic_vector(Ds);
- elsif(sw(7) = '1')then--nickles
- -- Bs<="000101";
- Ds<= Ds + B"000101";
- --Ds<=std_logic_vector(Ds);
- elsif(sw(8) = '1')then--dimes
- --Cs<="001010";
- Ds<= Ds + B"001010";
- --Ds<=std_logic_vector(Ds);
- else
- state_next<=rdy;
- end if;
- when cancel =>
- Ds <= Ds - Ds;
- --Ds <= std_logic_vector(Ds);
- when vend =>
- if(sw(0) = '1')then--chip1
- Ds <= Ds - B"110010";
- -- Ds<=std_logic_vector(Ds);
- state_next<=rdy;
- elsif(sw(1) = '1')then--chip2
- Ds<= Ds - B"110010";
- --Ds<=std_logic_vector(Ds);
- state_next<=rdy;
- elsif(sw(2) = '1')then--candy1
- Ds<= Ds - B"111100";
- --Ds<=std_logic_vector(Ds);
- state_next<=rdy;
- elsif(sw(3) = '1')then--candy2
- Ds<= Ds - B"111100";
- --Ds<=std_logic_vector(Ds);
- state_next<=rdy;
- elsif(sw(4) = '1')then--candy3
- Ds<= Ds - B"111100";
- --Ds<=std_logic_vector(Ds);
- state_next<=rdy;
- else
- state_next<=err;
- end if;
- when err =>
- if( Ds < "111100")then
- state_next<=rdy;
- else
- state_next<=rdy;
- end if;
- end case;
- end process;
- process(all)
- begin
- case state is
- when rdy =>
- if(Ds ="000000")then
- seg1<=r;
- seg2<=e;
- seg3<=a;
- seg4<=d;
- seg5<=y;
- seg6<=blank;
- elsif(Ds = "000101")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s0;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "001010")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s1;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "001111")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s1;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "010100")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s2;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "011001")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s2;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "011110")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s3;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "100011")then--35
- seg1<=dash;
- seg2<=dash;
- seg3<=s3;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "101000")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s4;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "101101")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s4;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "110010")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s5;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "110111")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s5;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "111100")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s6;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- else
- seg1<=dash;
- seg2<=dash;
- seg3<=s0;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- end if;
- when vend =>
- if(choose(0) = '1')then
- seg1<=u;
- seg2<=e;
- seg3<=n;
- seg4<=d;
- seg5<=s1;
- seg6<=blank;
- led<="00001";
- --choose(0)<= '0';
- elsif(choose(1) = '1')then
- seg1<=u;
- seg2<=e;
- seg3<=n;
- seg4<=d;
- seg5<=s2;
- seg6<=blank;
- led<="00010";
- --choose(1)<= '0';
- elsif(choose(2) = '1')then
- seg1<=u;
- seg2<=e;
- seg3<=n;
- seg4<=d;
- seg5<=s3;
- seg6<=blank;
- led<="00100";
- --choose(2)<= '0';
- elsif(choose(3) = '1')then
- seg1<=u;
- seg2<=e;
- seg3<=n;
- seg4<=d;
- seg5<=s4;
- seg6<=blank;
- led<="01000";
- --choose(3)<= '0';
- elsif(choose(4) = '1')then
- seg1<=u;
- seg2<=e;
- seg3<=n;
- seg4<=d;
- seg5<=s5;
- seg6<=blank;
- led<="10000";
- --choose(4)<= '0';
- else
- seg1<=blank;
- seg2<=blank;
- seg3<=blank;
- seg4<=blank;
- seg5<=blank;
- seg6<=blank;
- led<="00000";
- end if;
- when cancel =>
- seg1<=c;
- seg2<=a;
- seg3<=n;
- seg4<=c;
- seg5<=e;
- seg6<=l;
- led<="11111";
- when err =>
- if(Ds < "110010")then
- if(Ds = "000101")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s0;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "001010")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s1;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "001111")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s1;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "010100")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s2;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "011001")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s2;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "011110")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s3;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "100011")then--35
- seg1<=dash;
- seg2<=dash;
- seg3<=s3;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "101000")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s4;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "101101")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s4;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "110010")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s5;
- seg4<=s0;
- seg5<=dash;
- seg6<=dash;
- elsif(Ds = "110111")then
- seg1<=dash;
- seg2<=dash;
- seg3<=s5;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- else
- seg1<=dash;
- seg2<=dash;
- seg3<=s5;
- seg4<=s5;
- seg5<=dash;
- seg6<=dash;
- end if;
- else
- seg1<=blank;
- seg2<=blank;
- seg3<=blank;
- seg4<=blank;
- seg5<=blank;
- seg6<=blank;
- end if;
- end case;
- end process;
- --register logics
- --process(clk, rstb)--1hrz
- -- begin
- -- -- reset
- -- if (rstb = '0') then
- -- cnt <= (others => '0');
- -- -- rising clk edge
- -- elsif (rising_edge(clk)) then---1hz
- -- if(cnt < delay - 1) then
- -- cnt <= cnt + 1;
- -- else
- -- cnt <= (others => '0');
- -- end if;
- -- end if;
- --end process;
- process(clk, rstb)--clk1hz
- begin
- -- reset
- if (rstb = '0') then
- state <= rdy;
- -- rising clk edge
- elsif (rising_edge(clk)) then--1hrz
- state <= state_next;
- end if;
- end process;
- process(rstb,clk)--slow clk
- begin
- if (rstb ='0') then
- clockcnt<=0;
- elsif rising_edge(clk) then
- clockcnt <= clockcnt+1;
- if clockcnt = 25000000 then
- clk1hz <= not clk1hz;
- clockcnt <=0;
- end if;
- end if;
- end process;
- end behavioral;
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