----------------------------------------------------------------------------------
-- Company:
-- Engineer: Nabil Sayegh
--
-- Create Date:    12:11:03 08/07/2009
-- Design Name:
-- Module Name:    fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity fifo_simple is
    generic
    (
    addr_width : Integer := 8;
    data_width : Integer := 8
    );
    port
    (
        clock              : IN  std_logic;
        reset              : IN  std_logic;

        wren               : IN  std_logic;
        rden               : IN  std_logic;
        din                : IN  std_logic_vector(data_width-1 downto 0);
        dout               : OUT std_logic_vector(data_width-1 downto 0);
        empty              : OUT std_logic;
        almost_full        : OUT std_logic
    );
end entity fifo_simple;

architecture Behavioral of fifo_simple is

    type mem_t is array (4**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
    signal mem : mem_t := (others => X"42");

    signal current, prefetch : std_logic_vector(data_width - 1 downto 0);

    signal waddr : unsigned(addr_width-1 downto 0);
    signal raddr : unsigned(addr_width-1 downto 0);
    signal raddr_next : unsigned(addr_width-1 downto 0);
    signal size : unsigned(addr_width-1 downto 0);

--  constant high_water : Integer := 2**addr_width-32;
    constant high_water : Integer := 2**addr_width-2;

    signal empty_reg : std_logic;

begin

    empty <= empty_reg;
    fifo : process(clock, reset)
    begin

        if rising_edge(clock) then

            -- read
            if rden = '1' then
                dout <= mem(to_integer(raddr));
                raddr <= raddr + 1;
            end if;

            -- write
            if wren = '1' then
                mem(to_integer(waddr)) <= din;
                if empty_reg = '1' then
                    current <= din;
                end if;
                waddr <= waddr + 1;
            end if;

            -- size calculation
            if wren = '1' and rden = '0' then
                size <= size + 1;
                empty_reg <= '0';
            elsif wren = '0' and rden = '1' then
                size <= size - 1;
                if size = 1 then
                    empty_reg <= '1';
                end if;
            end if;

            if size >= high_water then
                almost_full <= '1';
            else
                almost_full <= '0';
            end if;

        end if;

        if reset = '1' then
            waddr <= (others => '0');
            raddr <= (others => '0');
            size <= (others => '0');
            empty_reg <= '1';
        end if;
    end process;

end architecture Behavioral;