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-- Company:
-- Engineer:
--
-- Create Date:    09:27:10 04/05/2018
-- Design Name:
-- Module Name:    s400pp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity s400pp is
    Port (
           CLK100 : in  STD_LOGIC;
           adc_in : in  STD_LOGIC_VECTOR (8 downto 0);
           adc_out : out  STD_LOGIC_VECTOR (8 downto 0));
end s400pp;

architecture Behavioral of s400pp is
signal adc : STD_LOGIC_VECTOR (8 downto 0);
begin
--adc<=adc_in;
--adc<=adc+"110010000";
adc_out<=adc_in+"100000001";
end Behavioral;