dexmux24

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY demux24 IS port(
g, c, b, a : in std_logic;
y : out std_logic_vector(0 to 3)
);
END demux24;

ARCHITECTURE arch OF demux24 IS

BEGIN
    process(a, b, c, g) is
            variable i: std_logic_vector(0 to 1);
        begin
            y <= "1111";
            i := (b, a);

            if(g = '0') then
                case i is
                    when "00" =>
                        y(0) <= not c;
                    when "01" =>
                        y(1) <= not c;
                    when "10" =>
                        y(2) <= not c;
                    when "11" =>
                        y(3) <= not c;
                    when others =>
                        y(0) <= c;
                end case;
            end if;
        end process;
END arch;