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simul

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Jun 25th, 2018
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VHDL 0.94 KB | None | 0 0
  1.  sk1 <= "01010101", "11001100" after 50 ns, "11001100" after 100 ns, "11001100" after 150 ns, "01010101" after 200 ns, "01010101" after 250 ns, "01010101" after 300 ns, "01010101" after 350 ns;
  2.         sk2 <= "01010101", "11001100" after 50 ns, "11001100" after 100 ns, "11001100" after 150 ns, "01010101" after 200 ns, "01010101" after 250 ns, "01010101" after 300 ns, "01010101" after 350 ns;
  3.         sk3 <= "01010101", "11001100" after 50 ns, "11001100" after 100 ns, "11001100" after 150 ns, "01010101" after 200 ns, "01010101" after 250 ns, "01010101" after 300 ns, "01010101" after 350 ns;
  4.         sclkin <= '0', '1' after 25 ns, '0' after 50 ns, '1' after 75 ns, '0' after 100 ns, '1' after 125 ns, '0' after 150 ns, '1' after 175 ns, '0' after 200 ns, '1' after 225 ns, '0' after 250 ns, '1' after 275 ns, '0' after 300 ns, '1' after 325 ns, '0' after 350 ns, '1' after 375 ns, '0' after 400 ns, '1' after 425 ns, '0' after 450 ns, '1' after 475 ns;
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