library ieee;
use ieee.std_logic_1164.all;
entity Extensor is
    port
    (
        X,Y,Z,a,b           : in STD_logic_vector(3 downto 0);
        Ia,Ib,cin           : out STD_logic_vector(3 downto 0)
    );
end Extensor;

architecture Estrutural of Extensor is
begin
    Ia <= (not(x) and a) or (x and y and z and not(a));
    Ib <= (not(x) and not(y) and not(z) and b) or (not(x) and not(y) and z and not(b));
    cin(0) <= (y(0) and not(z(0)) and not(a(0)) and b(0)) or (x(0) and not(y(0)) and a(0) and b(0)) or (not(x(0)) and y(0) and not(z(0))) or (not(x(0)) and not(y(0)) and z(0)) or (not(y(0)) and z(0) and b(0)) or (not (y(0)) and z(0) and a(0)) or (y(0) and not(z(0)) and a(0) and not(b(0)));
    cin(3 downto 1) <= (x(3 downto 1) and y(3 downto 1) and not(z(3 downto 1)) and not(a(3 downto 1)) and b(3 downto 1)) or (x(3 downto 1) and y(3 downto 1) and not(z(3 downto 1)) and a(3 downto 1) and not(b(3 downto 1))) or (x(3 downto 1) and not(y(3 downto 1)) and z(3 downto 1) and b(3 downto 1)) or (x(3 downto 1) and not (y(3 downto 1)) and z(3 downto 1) and a(3 downto 1)) or (x(3 downto 1) and not (y(3 downto 1)) and a(3 downto 1) and b(3 downto 1));
end Estrutural;
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SomadorCompleto is
    port
    (
        a,b,ci              : in STD_logic_vector(3 downto 0);
        co,s                : out STD_logic_vector(3 downto 0)
    );
end SomadorCompleto;

architecture Estrutural of SomadorCompleto is
begin
    co <= (a and b) or (a and ci) or (b and ci);
    s <= (a xor b xor ci);
end Estrutural;
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SomadorCompleto4B is
    port
    (
        a,b,ci              : in STD_logic_vector(3 downto 0);
        s                   : out STD_logic_vector(3 downto 0);
        cof                 : out STD_logic
    );
end SomadorCompleto4B;

architecture Estrutural of SomadorCompleto4B is
signal coci : STD_logic_vector(3 downto 1);
component SomadorCompleto port
    (
        a,b,ci              : in STD_logic;
        s,co                : out STD_logic
    );
end component SomadorCompleto;
begin
    SomadorCompleto0 : SomadorCompleto port map(a(0),b(0),ci(0),s(0),coci(1));
    SomadorCompleto1 : SomadorCompleto port map(a(1),b(1),ci(1) or coci(1),s(1),coci(2));
    SomadorCompleto2 : SomadorCompleto port map(a(2),b(2),ci(2) or coci(2),s(2),coci(3));
    SomadorCompleto3 : SomadorCompleto port map(a(3),b(3),ci(3) or coci(3),s(3),cof);
end Estrutural;
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ULA is
    port
    (
        X,Y,Z          : in STD_logic;
        A,B            : in STD_logic_vector(3 downto 0);
        S              : out STD_logic_vector(3 downto 0);
        Cout           : out STD_logic
    );
end ULA;

architecture Estrutural of ULA is
signal sIa : STD_logic_vector(3 downto 0);
signal sIb : STD_logic_vector(3 downto 0);
signal scin : STD_logic_vector(3 downto 0);
component Extensor port
    (
        X,Y,Z               : in STD_logic;
        A,B                 : in STD_logic_vector(3 downto 0);
        Ia,Ib,cin           : out STD_logic_vector(3 downto 0)
    );
end component Extensor;
component SomadorCompleto4B port
    (
        a,b,ci              : in STD_logic_vector(3 downto 0);
        s               : out STD_logic_vector(3 downto 0);
        cof                 : out STD_logic
    );
end component SomadorCompleto4B;

begin
    Ext: Extensor port map (X,Y,Z,A,B,sIa,sIb,scin);
    SC: SomadorCompleto4B port map (sIa,sIb,scin,s,Cout);
end Estrutural;