----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    11:31:25 12/14/2011
-- Design Name:
-- Module Name:    cpu_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cpu_top is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iINSTR : in  STD_LOGIC_VECTOR (14 downto 0);
           iDATA : in  STD_LOGIC_VECTOR (15 downto 0);
           oPC : out  STD_LOGIC_VECTOR (15 downto 0);
           oDATA : out  STD_LOGIC_VECTOR (15 downto 0);
           oADDR : out  STD_LOGIC_VECTOR (15 downto 0);
           oWE : out  STD_LOGIC;
              oR0, oR1, oR2, oR3, oR4, oR5, oR6, oR7 : out  STD_LOGIC_VECTOR (15 downto 0);
              oPHASE : out  STD_LOGIC_VECTOR (1 downto 0)
              );
end cpu_top;

architecture Behavioral of cpu_top is
component reg is
   generic (Sirina: integer :=16);
   Port (
           iCLK   : in   STD_LOGIC;
           inRST  : in   STD_LOGIC;
           iD     : in   STD_LOGIC_VECTOR (Sirina-1 downto 0);
           iWE    : in   STD_LOGIC;
           oQ     : out  STD_LOGIC_VECTOR (Sirina-1 downto 0));
    end component;
-----------------------------------------------------------------
    component mux is
    Port ( iD0 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD1 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD2 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD3 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD4 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD5 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD6 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD7 : in  STD_LOGIC_VECTOR (15 downto 0);
           iD8 : in  STD_LOGIC_VECTOR (15 downto 0);
           iSEL : in  STD_LOGIC_VECTOR (3 downto 0);
           oQ : out  STD_LOGIC_VECTOR (15 downto 0));
    end component;
-----------------------------------------------------------------
    component cnt is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iD : in  STD_LOGIC_VECTOR (15 downto 0);
           iEN : in  STD_LOGIC;
           iLOAD : in  STD_LOGIC;
           oQ : out  STD_LOGIC_VECTOR (15 downto 0));
    end component;
-----------------------------------------------------------------
    component alu is
    Port ( iA : in  STD_LOGIC_VECTOR (15 downto 0);
           iB : in  STD_LOGIC_VECTOR (15 downto 0);
           iSEL : in  STD_LOGIC_VECTOR (3 downto 0);
           oC : out  STD_LOGIC_VECTOR (15 downto 0);
           oZERO : out  STD_LOGIC;
           oSIGN : out  STD_LOGIC;
           oCARRY : out  STD_LOGIC);
    end component;
-----------------------------------------------------------------
    component control_unit is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iINSTR : in  STD_LOGIC_VECTOR (14 downto 0);
           oREG_WE : out  STD_LOGIC_VECTOR (7 downto 0);
           oA_WE : out  STD_LOGIC;
           oB_WE : out  STD_LOGIC;
           oC_WE : out  STD_LOGIC;
           oIR_WE : inout  STD_LOGIC;
           oPC_WE : out  STD_LOGIC;
           oPC_LOAD : out  STD_LOGIC;
           oMUXA_SEL : out  STD_LOGIC_VECTOR (3 downto 0);
           oMUXB_SEL : out  STD_LOGIC_VECTOR (3 downto 0);
           oALU_SEL : out  STD_LOGIC_VECTOR (3 downto 0);
           oMEM_WE : out  STD_LOGIC;
           oPC_IN : out  STD_LOGIC_VECTOR (15 downto 0);
           iZERO : in  STD_LOGIC;
           iSIGN : in  STD_LOGIC;
           iCARRY : in  STD_LOGIC;
              oPHASE : out STD_LOGIC_VECTOR(1 downto 0)
              );
    end component;

    --INTERNI SIGNALI
        signal sCARRY : STD_LOGIC;
        signal sZERO  : STD_LOGIC;
        signal sSIGN  : STD_LOGIC;
          signal sPHASE : STD_LOGIC_VECTOR(1 downto 0);

        signal sIR    : STD_LOGIC_VECTOR(14 downto 0);

        signal sREG_WE: STD_LOGIC_VECTOR (7 downto 0);
        signal sPC_IN : STD_LOGIC_VECTOR(15 downto 0);
        signal sA_WE  : STD_LOGIC;
        signal sB_WE  : STD_LOGIC;
        signal sC_WE  : STD_LOGIC;
        signal sIR_WE : STD_LOGIC;
        signal sPC_EN : STD_LOGIC;
        signal sPC_LOAD:STD_LOGIC;

        signal sMUXA_SEL : STD_LOGIC_VECTOR (3 downto 0);
        signal sMUXB_SEL : STD_LOGIC_VECTOR (3 downto 0);
        signal sALU_SEL  : STD_LOGIC_VECTOR (3 downto 0);
        signal sWE : STD_LOGIC;
        signal sDATA  : STD_LOGIC_VECTOR (15 downto 0);

        -- Interni signali za izlaze iz registara
        signal sR0 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR1 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR2 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR3 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR4 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR5 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR6 : STD_LOGIC_VECTOR(15 downto 0);
        signal sR7 : STD_LOGIC_VECTOR(15 downto 0);

        -- Interni signali za izlaze iz multipleksera
        signal sMUXA : STD_LOGIC_VECTOR(15 downto 0);
        signal sMUXB : STD_LOGIC_VECTOR(15 downto 0);

        -- Interni signali za izlaze iz registara A i B
        signal sA_OUT : STD_LOGIC_VECTOR(15 downto 0);
        signal sB_OUT : STD_LOGIC_VECTOR(15 downto 0);

        -- Interni signali za aritmeticko logicku jedinicu
        signal sRESULT : STD_LOGIC_VECTOR(15 downto 0);

        -- Interni signali za realizaciju registra ZSC
        signal sS : STD_LOGIC;
        signal sC : STD_LOGIC;
        signal sZ : STD_LOGIC;

        -- Interni signali za programski brojac
        signal sPC : STD_LOGIC_VECTOR(15 downto 0);
begin
--  Izlazi iz top-a

        oADDR   <= sMUXB;
        oDATA   <= sDATA;
        oPC     <= sPC;
          oWE    <= sWE;

          oR0 <= sR0;
          oR1 <= sR1;
          oR2 <= sR2;
          oR3 <= sR3;
          oR4 <= sR4;
          oR5 <= sR5;
          oR6 <= sR6;
          oR7 <= sR7;

          oPHASE <= sPHASE;

--  Aritmeticko Logicka Jedinica

        iALU:alu port map (
                iA     => sA_OUT,
                iB     => sB_OUT,
                iSEL   => sALU_SEL,
                oC     => sRESULT,
                oZERO  => sZ,
                oSIGN  => sS,
                oCARRY => sC
        );

-- Registar C

            iC:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sRESULT,
                iWE => sC_WE,
                oQ => sDATA
        );

--  Flip-flop ZSC

        process (iCLK,inRST) begin
                if(inRST='0') then
                        sZERO <='0';
                        sSIGN <='0';
                        sCARRY <='0';
                elsif(iCLK'event and iCLK='1') then
                        if(sC_WE='1') then
                                sZERO <= sZ;
                                sSIGN <= sS;
                                sCARRY <= sC;

                        end if;

                end if;
        end process;

-- Control unit

        icontrol_unit:control_unit port map (
        iCLK      => iCLK,
        inRST     => inRST,
        iCARRY    => sCARRY,
        iZERO     => sZERO,
        iSIGN     => sSIGN,
        iINSTR    => sIR,     --Iz instrukcijskog registra
        oREG_WE   => sREG_WE,
        oA_WE     => sA_WE,
        oB_WE     => sB_WE,
        oC_WE     => sC_WE,
        oIR_WE    => sIR_WE,
        oPC_IN    => sPC_IN,
        oPC_WE    => sPC_EN,
        oPC_LOAD  => sPC_LOAD,
        oMUXA_SEL => sMUXA_SEL,
        oMUXB_SEL => sMUXB_SEL,
        oALU_SEL  => sALU_SEL,
        oMEM_WE   => sWE,
          oPHASE => sPHASE

        );

-- Instrukcijski registar

        iIR_reg:reg generic map(Sirina => 15)
        port map(
                iCLK => iCLK,
                inRST => inRST,
                iD  =>iINSTR,
                iWE => sIR_WE,
                oQ =>sIR
        );

-- Registri R0 - R7

        iR0_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(0),
                oQ => sR0
        );


        iR1_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(1),
                oQ => sR1
        );


        iR2_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(2),
                oQ => sR2
        );

        iR3_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(3),
                oQ => sR3
        );

        iR4_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(4),
                oQ => sR4
        );

        iR5_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(5),
                oQ => sR5
        );

        iR6_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(6),
                oQ => sR6
        );

        iR7_reg:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sDATA,
                iWE => sREG_WE(7),
                oQ => sR7
        );

--  Multiplekseri A i B

        iMUXA:mux port map (
                iD0 => sR0,
                iD1 => sR1,
                iD2 => sR2,
                iD3 => sR3,
                iD4 => sR4,
                iD5 => sR5,
                iD6 => sR6,
                iD7 => sR7,
                iD8 => iDATA,
                iSEL => sMUXA_SEL,
                oQ => sMUXA
        );

        iMUXB:mux port map (
                iD0 => sR0,
                iD1 => sR1,
                iD2 => sR2,
                iD3 => sR3,
                iD4 => sR4,
                iD5 => sR5,
                iD6 => sR6,
                iD7 => sR7,
                iD8 => iDATA,
                iSEL => sMUXB_SEL,
                oQ => sMUXB
        );

--  Registri A i B

        iA:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sMUXA,
                iWE => sA_WE,
                oQ => sA_OUT
        );

        iB:reg port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sMUXB,
                iWE => sB_WE,
                oQ => sB_OUT
        );

--  Programski Brojac

        iPC:cnt port map (
                iCLK => iCLK,
                inRST => inRST,
                iD => sPC_IN,
                iEN => sPC_EN,
                iLOAD => sPC_LOAD,
                oQ => sPC
        );

end Behavioral;