VHDL - T Flip Flop

--- Author: Matej Arlović, 2018.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity flipflop_t is
    port(
        T, cp: in STD_LOGIC;
        Q, Qn: out STD_LOGIC
    );
end flipflop_t;

architecture Behavioral of flipflop_t is
    signal temp: STD_LOGIC;
begin
    process (T,cp)
    begin
        if(T = '1') then
            temp <= '0';
        elsif(cp'EVENT and cp = '1') then
            temp <= not(temp);
        end if;
    end process;
    Q <= temp;
    Qn <= not(temp);
end Behavioral;

--- Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY flipflop_t_w IS
END flipflop_t_w;

ARCHITECTURE behavior OF flipflop_t_w IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT flipflop_t
    PORT(
         T : IN  std_logic;
         cp : IN  std_logic;
         Q : OUT  std_logic;
            Qn: OUT std_logic
        );
    END COMPONENT;


   --Inputs
   signal T : std_logic := '0';
   signal cp : std_logic := '0';

    --Outputs
   signal Q : std_logic;
    signal Qn: std_logic;
   constant cp_period : time := 200 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: flipflop_t PORT MAP (
          T => T,
          cp => cp,
          Q => Q,
             Qn => Qn
        );

   -- Clock process definitions
   cp_process :process
   begin
        cp <= '0';
        wait for cp_period/2;
        cp <= '1';
        wait for cp_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
        T <= '1';
        wait for 100ns;
        T <= '0';
        wait for 100ns;
   end process;
END;