JK FLIP-FLOP SYNC

-- design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity jk_flipflop_sync is
    port(J, K, clock : in std_logic;
         Q, Qn : out std_logic);
end entity jk_flipflop_sync;

architecture jk_flipflop_sync_arch of jk_flipflop_sync is
begin
    process(clock)
    begin
        if(clock'event and clock = '1') then
          if(J = '0' and K = '0') then
              Q <= Q;
              Qn <= Qn;
          elsif(J = '0' and K = '1') then
              Q <= '0';
              Qn <= '1';
          elsif(J = '1' and K = '0') then
              Q <= '1';
              Qn <= '0';
          elsif(J = '1' and K = '1') then
              Q <= Qn;
              Qn <= Q;
          else
              Q <= 'Z';
              Qn <= 'Z';
          end if;
        end if;
    end process;
end architecture jk_flipflop_sync_arch;

-- testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity jk_flipflop_sync_tb is
end entity jk_flipflop_sync_tb;

architecture jk_flipflop_sync_tb_arch of jk_flipflop_sync_tb is
    signal J, K, clock, Q, Qn : std_logic;
begin
    DUT1 : entity work.jk_flipflop_sync(jk_flipflop_sync_arch)
           port map(J, K, clock, Q, Qn);
    CLOCK_PROCESS : process
    begin
        clock <= '0'; wait for 10ns;
        clock <= '1'; wait for 10ns;
    end process CLOCK_PROCESS;
    STIMULUS : process
    begin
        J <= '0'; K <= '0'; wait for 10ns;
        J <= '1'; K <= '0'; wait for 10ns;
        J <= '0'; K <= '1'; wait for 10ns;
        J <= '1'; K <= '1'; wait for 10ns;
        J <= 'X'; K <= 'X'; wait for 10ns;
    end process STIMULUS;
end architecture jk_flipflop_sync_tb_arch;