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Single Port Ram with separate R/W

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May 30th, 2018
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VHDL 0.94 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity single_port_ram_rw is
  6. generic(
  7.     address_length: natural := 8;
  8.     data_length: natural := 8
  9. );
  10. port(
  11.     clock: in std_logic;
  12.     read_enable: in std_logic;
  13.     write_enable: in std_logic;
  14.     address: in std_logic_vector((address_length - 1) downto 0);
  15.     data_input: in std_logic_vector ((data_length - 1) downto 0);
  16.     data_output: out std_logic_vector ((data_length - 1) downto 0)
  17. );
  18. end single_port_ram_rw;
  19.  
  20. architecture arch of single_port_ram_rw is
  21.     type ram_type is array (0 to (2**(address_length) -1)) of std_logic_vector((data_length - 1) downto 0);
  22.     signal ram: ram_type;
  23. begin
  24.  
  25. process(clock) is
  26. begin
  27.     if rising_edge(clock)then
  28.         if(read_enable = '1') then
  29.             data_output <= ram(conv_integer(unsigned(address)));
  30.         elsif (write_enable = '1') then
  31.             ram(conv_integer(unsigned(address))) <= data_input;
  32.         end if;    
  33.     end if;
  34. end process;
  35.  
  36. end arch;
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