Single Port Ram with combined R/W

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity single_port_ram_rwc is
generic(
    address_length: natural := 8;
    data_length: natural := 8
);
port(
    clock: in std_logic;
    rw_enable: in std_logic;
    mem_enable: in std_logic;
    address: in std_logic_vector((address_length - 1) downto 0);
    data_input: in std_logic_vector ((data_length - 1) downto 0);
    data_output: out std_logic_vector ((data_length - 1) downto 0)
);
end single_port_ram_rwc;

architecture arch of single_port_ram_rwc is
    type ram_type is array (0 to (2**(address_length) -1)) of std_logic_vector((data_length - 1) downto 0);
    signal ram: ram_type;
    signal temp_address: std_logic_vector((address_length - 1) downto 0);
begin

process(clock) is
begin
    if rising_edge(clock)and mem_enable = '1' then
        if(rw_enable = '0') then
            temp_address <= address;
        elsif (rw_enable = '1') then
            ram(conv_integer(unsigned(address))) <= data_input;
        end if;
        data_output <= ram(conv_integer(unsigned(temp_address)));
    end if;

end process;

end arch;