2. ZAD

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    18:37:34 12/07/2011
-- Design Name:
-- Module Name:    led01 - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led01 is
    port (  --2. ZADATAK
            clk : in std_logic; -- signal takta
            reset : in std_logic; -- signal reseta
            ld7 : out std_logic; -- signal za upravljanje LED LD7
            );
end led01;

architecture RTL of led01 is

    --2. ZADATAK
    signal brojilo: std_logic_vector(25 downto 0);



begin



    --2. ZADATAK
    process (clk) is
    begin
        if rising_edge(clk) then
            if reset='1' then
                brojilo<=(others => '0');
            else
                brojilo<=brojilo+1;
            end if;
        end if;
    end process;

    ld7<=brojilo(25);


end RTL;