automat

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-- Company:
-- Engineer:
--
-- Create Date:    14:10:03 11/22/2011
-- Design Name:
-- Module Name:    automat - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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PACKAGE TIPOVI IS
    TYPE tSTANJA IS (S0, S1, S2, S3);
END TIPOVI;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.TIPOVI.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity automat is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iW : in  STD_LOGIC_VECTOR (1 downto 0);
           oZ : out  STD_LOGIC);
end automat;

architecture Behavioral of automat is
    signal Z0: STD_LOGIC := '0';
    signal Z1: STD_LOGIC := '1';
    signal sSTANJE, sSLEDECE_STANJE: tSTANJA;

    --signal W0: STD_LOGIC_VECTOR(1 downto 0):= "00";
    --signal W1: STD_LOGIC_VECTOR(1 downto 0):= "01";
    --signal W2: STD_LOGIC_VECTOR(1 downto 0):= "10";

begin
    process(iW, sSTANJE) begin
        case sSTANJE is

        ---stanje S0 = "00"
        when S0 =>
            case iW is
            when "00" => sSLEDECE_STANJE <= S1; oZ <= Z0;
            when "01" => sSLEDECE_STANJE <= S1; oZ <= Z1;
            when "10" => sSLEDECE_STANJE <= S2; oZ <= Z1;
            when others => sSLEDECE_STANJE <= sSLEDECE_STANJE; oZ <= Z1;
        end case;
        ---stanje S1 = "01"
        when S1 =>
            case iW is
            when "00" => sSLEDECE_STANJE <= S0;  oZ<= Z1;
            when "01" => sSLEDECE_STANJE <= S1; oZ<= Z0;
            when "10" => sSLEDECE_STANJE <= S1; oZ <= Z0;
            when others => sSLEDECE_STANJE <= sSLEDECE_STANJE; oZ <= Z0;
        end case;
        ----stanje S2 = "10"
        when S2 =>
        case iW is
            when "00" => sSLEDECE_STANJE <= S3; oZ<=Z0;
            when "01" => sSLEDECE_STANJE <= S1; oZ<= Z1;
            when "10" => sSLEDECE_STANJE <=S0; oZ <=Z1;
            when others => sSLEDECE_STANJE <= sSLEDECE_STANJE; oZ <= Z1;
        end case;
        ---stanje S3 = "11"
        when S3 =>
        case iW is
            when "00" => sSLEDECE_STANJE <= S0; oZ<= Z1;
            when "01" => sSLEDECE_STANJE <=S1; oZ <= Z0;
            when "10" => sSLEDECE_STANJE <= S0; oZ <= Z0;
            when others => sSLEDECE_STANJE <= sSLEDECE_STANJE; oZ <= Z0;
        end case;
    end case;
end process;


--- flip flopovi za pamcenje koda trenutnog stanja
        ---reset je sinhron, u listi osetljivosi nema inRST
        process(iCLK) begin
            if(iCLK'event and iCLK= '1') then
                if(inRST = '1') then
                    sSTANJE <= S0;
                else
            sSTANJE<= sSLEDECE_STANJE;
            end if;
        end if;
    end process;




end Behavioral;