20141002_KUAS_Verilog_FullAdder_8Bit(DataFlow)

/***********************************************/
/** 20141002 8-Bit Full Adder (Use Data Flow) **/
/** Maker  : Yan                              **/
/** E-Mail : [email protected]            **/
/** Date   : 2014/10/02 pm.10:40              **/
/***********************************************/

module FullAdder_8Bit(input1, input2, carryIn, sum, carryOut);
    parameter   BitLenght = 8;
    input       [BitLenght - 1 : 0] input1, input2;
    input       carryIn;
    output      [BitLenght - 1 : 0] sum;
    output      carryOut;

    assign      {carryOut, sum} = input1 + input2 + carryIn;
endmodule