--- add1bit.vhd

library ieee;
use ieee.std_logic_1164.all;

entity add1bit is
    Port(
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        c_in: in STD_LOGIC;
        sum: out STD_LOGIC;
        c_out: out STD_LOGIC
    );
end add1bit;


architecture behaviour of add1bit is
begin
    sum <= (a xor b) xor c_in;
    c_out <= (a and b) or (c_in and (a xor b));
end behaviour;

-------------------------------------------------------------------

--add4bit.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity add4bit is
    Port(
        a_vec: in STD_LOGIC_VECTOR(3 downto 0);
        b_vec: in STD_LOGIC_VECTOR(3 downto 0);
        cin_vec: in STD_LOGIC;
        sum_vec: out STD_LOGIC_VECTOR(3 downto 0);
        cout_vec: out STD_LOGIC
    );
end add4bit;


architecture behaviour of add4bit is
component add1bit
    Port(
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        c_in: in STD_LOGIC;
        sum: out STD_LOGIC;
        c_out: out STD_LOGIC
    );
end component;

signal c1, c2, c3: STD_LOGIC;

begin
    stage0: add1bit port map(
        a=>a_vec(0),
        b=>b_vec(0),
        c_in=>cin_vec,
        sum=>sum_vec(0),
        c_out=>c1
    );
    stage1: add1bit port map(
        a=>a_vec(1),
        b=>b_vec(1),
        c_in=>c1,
        sum=>sum_vec(1),
        c_out=>c2
    );
    stage2: add1bit port map(
        a=>a_vec(2),
        b=>b_vec(2),
        c_in=>c2,
        sum=>sum_vec(2),
        c_out=>c3
    );
    stage3: add1bit port map(
        a=>a_vec(3),
        b=>b_vec(3),
        c_in=>c3,
        sum=>sum_vec(3),
        c_out=>cout_vec
    );
end behaviour;

-------------------------------------------------

--hex_decoder

library ieee;
use ieee.std_logic_1164.all;

entity hexdecoder is
    Port (
        num: in STD_LOGIC_VECTOR(0 to 3);
        leds: out STD_LOGIC_VECTOR(0 to 7)
    );
end hexdecoder;

--
--     111
--     2 3
--     243
--     5 6
--     777 8
--

architecture Behaviour of hexdecoder is
begin
    with num select leds <=
        "00000000" when "0000",
        "00000000" when "0001",
        "00000000" when "0010",
        "00000000" when "0011",
        "00000000" when "0100",
        "00000000" when "0101",
        "00000000" when "0110",
        "00000000" when "0111",
        "00000000" when "1000",
        "00000000" when "1001",
        "00000000" when "1010",
        "00000000" when "1011",
        "00000000" when "1100",
        "00000000" when "1101",
        "00000000" when "1110",
        "00000000" when "1111";
end Behaviour;