comp_phase

------------------------------------------------------
--               DETECT UP FRONT
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity detect_front is
  port(E ,reset ,clk : in std_logic;
        Ft_mt : out std_logic);
end detect_front;

architecture arch_detect_front of detect_front is
type me_states is (E_0, E_1, E_2);
signal etat_cr, etat_sv : me_states;
begin
process(clk,reset)
    begin
        if reset = '1' then etat_cr <= E_0;
        elsif (rising_edge(clk)) then etat_cr <= etat_sv;
        end if;
end process;

process( etat_cr, E)
    begin
        etat_sv <= etat_cr; Ft_mt <= '0';
        case etat_cr is
            when E_0 => if E = '1' then etat_sv <= E_1; end if;
            when E_1 => etat_sv <= E_2; Ft_mt <= '1';
            when E_2 => if E = '0' then etat_sv <= E_0; end if;
        end case;
end process;

end arch_detect_front;


------------------------------------------------------
--                   COMP PHASE
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ME_comp_phase is
  port(E,S,reset,clk : in std_logic;
        AV, AR : out std_logic);
end ME_comp_phase;

architecture arch_ME_comp_phase of ME_comp_phase is
type me_states is (EN_PHASE, AVANCE, RETARD);
signal etat_cr, etat_sv : me_states;
begin
process(clk,reset)
    begin
        if reset = '1' then etat_cr <= EN_PHASE;
        elsif (rising_edge(clk)) then etat_cr <= etat_sv;
        end if;
end process;

process(etat_cr,S,E)
    begin
        etat_sv <= etat_cr; AV <= '0'; AR <= '0';
        case etat_cr is
            when EN_PHASE => if (S = '0' and E = '1') then etat_sv <= AVANCE;
                            elsif (S = '1' and E = '0') then etat_sv <= RETARD;
                            end if;
            when AVANCE => AV <= '1';
                            if S = '1' then etat_sv <= EN_PHASE;
                            end if;
            when RETARD => AR <= '1';
                            if E = '1' then etat_sv <= EN_PHASE;
                            end if;
        end case;
end process;

end architecture arch_ME_comp_phase;

------------------------------------------------------
--                COMPARATEUR PHASE
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.all;

entity comp_phase is
  port(Top_0,Top_synchro,reset,clk : in std_logic;
        AV, AR : out std_logic);
end comp_phase;

architecture arch_comp_phase of comp_phase is
signal Ft_Top_0 : std_logic;
signal Ft_Top_Synchro : std_logic;
begin
DETEC1 : entity detect_front port map(
    E => Top_0,
    reset => reset,
    clk => clk,
    Ft_mt => Ft_Top_0);

DETEC2 : entity detect_front port map(
    E => Top_synchro,
    reset => reset,
    clk => clk,
    Ft_mt => Ft_Top_Synchro);

COMP : entity ME_comp_phase port map(
    E => Ft_Top_0,
    S => Ft_Top_Synchro,
    reset => reset,
    clk => clk,
    AV => AV,
    AR => AR);

end architecture arch_comp_phase;