library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--define adder
entity adder is

--wbit adder
generic (w : integer :=16);
port (
a,b : in std_logic_vector (w-1 downto 0);
c : out std_logic_vector (w-1 downto 0)
);

end entity;

architecture add of adder is

begin

--Add a+b and output to c
c <= a+b;




end architecture;