VHDL axis_i2s2

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-- Company:
-- Engineer:
--
-- Create Date: 03/30/2019 11:21:45 PM
-- Design Name:
-- Module Name: i2s_axis - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity i2s_axis is
    Port ( sys_clock : in STD_LOGIC;
           axis_reset_n : in STD_LOGIC;
           tx_axis_s_data : in STD_LOGIC_VECTOR (31 downto 0);
           tx_axis_s_valid : in STD_LOGIC;
           tx_axis_s_ready : out STD_LOGIC;
           tx_axis_s_last : in STD_LOGIC;
           rx_axis_m_data : out STD_LOGIC_VECTOR (31 downto 0);
           rx_axis_m_valid : out STD_LOGIC;
           rx_axis_m_ready : in STD_LOGIC;
           rx_axis_m_last : out STD_LOGIC;
           tx_mclk : out STD_LOGIC;
           tx_lrck : out STD_LOGIC;
           tx_sclk : out STD_LOGIC;
           tx_sdout : out STD_LOGIC;
           rx_mclk : out STD_LOGIC;
           rx_lrck : out STD_LOGIC;
           rx_sclk : out STD_LOGIC;
           rx_sdin : in STD_LOGIC);
end i2s_axis;

architecture Behavioral of i2s_axis is

    --Output signals
    signal tx_axis_s_ready_sig  : std_logic;
    signal rx_axis_m_valid_sig  : std_logic;
    signal rx_axis_m_last_sig   : std_logic;


    signal lrck             : std_logic;
    signal mclk             : std_logic;
    signal sclk             : std_logic;
    signal count            : std_logic_vector(8 downto 0) := (others => '0');
    signal axis_clk         : std_logic;
    signal tx_data_l        : std_logic_vector(31 downto 0) := (others => '0');
    signal tx_data_r        : std_logic_vector(31 downto 0) := (others => '0');
    signal tx_data_l_shift  : std_logic_vector(23 downto 0) := (others => '0');
    signal tx_data_r_shift  : std_logic_vector(23 downto 0) := (others => '0');
    signal din_sync_shift   : std_logic_vector(2 downto 0) := "000";
    signal din_sync         : std_logic;
    signal rx_data_l        : std_logic_vector(31 downto 0) := (others => '0');
    signal rx_data_r        : std_logic_vector(31 downto 0) := (others => '0');
    signal rx_data_l_shift  : std_logic_vector(23 downto 0) := (others => '0');
    signal rx_data_r_shift  : std_logic_vector(23 downto 0) := (others => '0');
begin

    axis_clk <= sys_clock;

    lrck <= count(8);
    sclk <= count(2);
    mclk <= axis_clk;
    tx_lrck <= lrck;
    tx_sclk <= sclk;
    tx_mclk <= mclk;
    rx_lrck <= lrck;
    rx_sclk <= sclk;
    rx_mclk <= mclk;


    --output signals
    tx_axis_s_ready <= tx_axis_s_ready_sig;
    rx_axis_m_valid <= rx_axis_m_valid_sig;
    rx_axis_m_last <= rx_axis_m_last_sig;

    process(axis_clk)
    begin
        if rising_edge(axis_clk) then
            count <= count + '1';
        end if;
    end process;

    process(axis_clk)
    begin
        if( rising_edge(axis_clk)) then
            if( axis_reset_n = '0') then
                tx_axis_s_ready_sig <= '0';
            elsif (tx_axis_s_ready_sig = '1') and (tx_axis_s_valid = '1') and (tx_axis_s_last = '1') then --end of packet, cannot accept data until current one has been transmitted
                tx_axis_s_ready_sig <= '0';
            elsif (count = "000000000") then  -- beginning of I2S frame, in order to avoid tearing, cannot accept data until frame complete
                tx_axis_s_ready_sig <= '0';
            elsif (count = "111000111") then -- end of I2S frame, can accept data
                tx_axis_s_ready_sig <= '1';
            end if;
        end if;
    end process;

    process(axis_clk)
    begin
        if( rising_edge(axis_clk)) then
            if (axis_reset_n = '0') then
                tx_data_r <= (others => '0');
                tx_data_l <= (others => '0');
            elsif (tx_axis_s_valid = '1' and tx_axis_s_ready_sig = '1') then
                if (tx_axis_s_last = '1') then
                    tx_data_r <= tx_axis_s_data;
                else
                    tx_data_l <= tx_axis_s_data;
                end if;
            end if;
        end if;
    end process;

    --/* I2S TRANSMIT SHIFT REGISTERS */
    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            if (count = "000000110") then
                tx_data_l_shift <= tx_data_l(23 downto 0);
                tx_data_r_shift <= tx_data_r(23 downto 0);
            elsif (count(2 downto 0) = "110") and (count(7 downto 3) >= "00001") and (count(7 downto 3) <= "11000") then
                if(count(8) = '1') then
                    tx_data_r_shift <= tx_data_r_shift(22 downto 0) & '0';
                else
                    tx_data_l_shift <= tx_data_l_shift(22 downto 0) & '0';
                end if;
            end if;
        end if;
    end process;

    process(count,tx_data_r_shift,tx_data_l_shift)
    begin
        if (count (7 downto 3) <= "11000") and (count(7 downto 3) >= "00001") then
            if(count(8) = '1') then
                tx_sdout <= tx_data_r_shift(23);
            else
                tx_sdout <= tx_data_l_shift(23);
            end if;
        else
            tx_sdout <= '0';
        end if;
    end process;

    --/* SYNCHRONIZE DATA IN TO AXIS CLOCK DOMAIN */
    din_sync <= din_sync_shift(2);
    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            din_sync_shift <= (din_sync_shift(1 downto 0) & rx_sdin);
        end if;
    end process;

    --/* I2S RECEIVE SHIFT REGISTERS */
    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            if(count (2 downto 0) = "011") and (count(7 downto 3) <= "11000") and (count(7 downto 3) >= "00001") then
                if (lrck = '1') then
                    rx_data_r_shift <= rx_data_r_shift(22 downto 0) & din_sync;
                else
                    rx_data_l_shift <= rx_data_l_shift(22 downto 0) & din_sync;
                end if;
            end if;
        end if;
    end process;

    --/* AXIS MASTER CONTROLLER */
    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            if(axis_reset_n = '0') then
                rx_data_l <= (others => '0');
                rx_data_r <= (others => '0');
            elsif (count = "111000111") and (rx_axis_m_valid_sig = '0') then
                rx_data_l <= ("00000000" & rx_data_l_shift);
                rx_data_r <= ("00000000" & rx_data_r_shift);
            end if;
        end if;
    end process;

    mux : process(rx_axis_m_last_sig, rx_data_r, rx_data_l)
    begin
        case rx_axis_m_last_sig is
            when '0' => rx_axis_m_data <= rx_data_l;
            when others => rx_axis_m_data <= rx_data_r;
        end case;
    end process;

    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            if(axis_reset_n = '0') then
                rx_axis_m_valid_sig <= '0';
            elsif (count = "111000111") and (rx_axis_m_valid_sig = '0') then
                rx_axis_m_valid_sig <= '1';
            elsif (rx_axis_m_valid_sig = '1') and (rx_axis_m_ready = '1') and (rx_axis_m_last_sig = '1') then
                rx_axis_m_valid_sig <= '0';
            end if;
        end if;
    end process;

    process(axis_clk)
    begin
        if (rising_edge(axis_clk)) then
            if(axis_reset_n = '0') then
                rx_axis_m_last_sig <= '0';
            elsif (count = "111000111") and (rx_axis_m_valid_sig = '0') then
                rx_axis_m_last_sig <= '0';
            elsif (rx_axis_m_valid_sig = '1') and (rx_axis_m_ready = '1') then
                rx_axis_m_last_sig <= not(rx_axis_m_last_sig);
            end if;
        end if;
    end process;


end Behavioral;