20210309_attiny13_timer

/*
 * 20210309_tiny13_timer.c
 *
 * Created: 2021-03-09 21:08:38
 * Author : uwezi
 */

// output on PB3, active high
// trigger on PB1 / INT0 active low

#define F_CPU 1200000UL

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#include <util/atomic.h>

volatile int16_t timeout = 0;
volatile int16_t settime = 0;

ISR(INT0_vect)
{
  timeout = settime;
  PORTB |= (1 << PB3);
}


// timer interrupt about 586/s
ISR(TIM0_OVF_vect)
{
  if (timeout > 0)
  {
    timeout --;
  }
  else
  {
    PORTB &= ~(1 << PB3);
  }
}


int main(void)
{
  int16_t dummy;
  DDRB   = (1 << PB3);
  // pull-up on PB1
  PORTB |= (1 << PB1);

  // ADC channel ADC2
  // internal ref
  // normal adjustment
  // 1:8 prescaler 150 kHz
  ADMUX  = (0 << REFS0) | (0 << ADLAR) | (1 << MUX1) | (0 << MUX0);
  ADCSRA = (1 << ADEN) | (0 << ADSC) | (0 << ADPS2) | (1 << ADPS1) | (1 << ADPS0);
  // first conversion
  ADCSRA |= (1 << ADSC);
  while (ADCSRA & (1 << ADSC)) { }
  settime = ADC;

  // timer 0 normal counting
  // 1:8 prescaler
  // 1.2 MHz / 8 / 256 = 585.9375 Hz
  TCCR0A = 0b00000000;
  TCCR0B = (0 << CS02) | (1 << CS01) | (0 << CS00);
  TIMSK0 = (1 << TOIE0);

  // falling edge triggers INT0
  MCUCR |= (1 << ISC01) | (0 << ISC00);
  GIMSK |= (1 << INT0);
  sei();

  while (1)
  {
    // update settime from resistor setting
    ADCSRA |= (1 << ADSC);
    while (ADCSRA & (1 << ADSC)) { }
    dummy = 7*settime + ADC;
    dummy = dummy / 8;
    ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
    {
      settime = dummy;
    }
    _delay_ms(100);
  }
}