solielios

ניסוי תבנית צבירה

Mar 9th, 2025
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VHDL 0.68 KB | None | 0 0
  1. library ieee;‎
  2. use ieee.std_logic_1164.all;‎
  3. ‎ ‎
  4. entity myOnes is
  5. port (din : in bit_vector(7 downto 0);‎
  6. ‎        y : out integer range 0 to 15);‎
  7. end;‎
  8. ‎ ‎
  9. architecture be of myOnes is
  10. begin
  11. ‎ ‎
  12. process(din)‎
  13. ‎    variable c : integer range 0 to 15 := 0;‎
  14. ‎    begin
  15. ‎    c:= 0;‎
  16. ‎    for i in 0 to 7 loop
  17. ‎        if din(i) = '1' then c := c + 1;‎
  18. ‎        else c := c;‎
  19. ‎        end if;‎
  20. ‎    end loop;‎
  21. ‎    y <= c;‎
  22. end process;‎
  23. ‎ ‎
  24. end be;‎
  25.  
  26.  
  27.  
  28. n, s = 0, 0‎
  29. while n >= 0:‎
  30. ‎    n = int(input("Enter a positive number: "))‎
  31. ‎    if n >= 0:‎
  32. ‎        s += n
  33. print(s)‎‏ ‏
  34.  
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