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hbinderup94

my_gates

May 27th, 2017
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VHDL 0.70 KB | None | 0 0
  1. ------ my_gates ------
  2. library ieee;
  3. use ieee.std_logic_1164.all;
  4.  
  5. entity my_gates is
  6. port(
  7.     a, b                        : in std_logic;
  8.     and_out, or_out, xor_out    : out std_logic);
  9. end my_gates;
  10.  
  11. architecture my_gates_arch of my_gates is
  12.  
  13.     -- funktion hvor xor af a og b returneres
  14.     function my_xor(a, b : std_logic) return std_logic is
  15.     begin
  16.         return a xor b;
  17.     end my_xor;
  18.    
  19.     -- procedure hvor "and og or" af a og b returneres
  20.     procedure and_or(signal a,b: in std_logic; signal and_out, or_out: out std_logic) is
  21.     begin
  22.         and_out <= a and b;
  23.         or_out  <= a or b;
  24.     end and_or;
  25.  
  26. begin
  27.  
  28.     -- proceduren og funktionen kaldes
  29.     xor_out <= my_xor(a,b);
  30.     and_or(a,b, and_out, or_out);    
  31.  
  32. end my_gates_arch;
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