top_module

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library machXO3;
use machXO3.all;

entity top_module is
    port (
        GSRN                :   in std_logic;

        rx_serial               :   in std_logic;
        trigger_from_awg        :   in std_logic;
        trigger_from_apd        :   in  std_logic;

        flag_start_experiment   :   out std_logic;
        flag_hard_limit         :   out std_logic;
        flag_nv_minus           :   out std_logic;

        trigger_to_awg          :   out std_logic;

        pulse_laser_1           :   out std_logic;
        pulse_laser_2           :   out std_logic;
        pulse_laser_3           :   out std_logic;
        pulse_laser_4           :   out std_logic;

        pulse_htm_dac_1         :   out std_logic;
        pulse_htm_dac_2         :   out std_logic;

        pulse_ni_gate           :   out std_logic
    );
end top_module;

architecture behaviour of top_module is

    component GSR
        port (  GSR : in std_logic);
    end component;

    COMPONENT OSCH
        GENERIC (NOM_FREQ: string := "53.2");
        PORT (  STDBY:IN std_logic;
                OSC:OUT std_logic;
                SEDSTDBY:OUT std_logic);
    END COMPONENT;

    attribute NOM_FREQ : string;
    attribute NOM_FREQ of OSCinst0 : label is "53.2";

    signal clk : std_logic;

    component tiptop_module
        generic (
            g_CLKS_PER_BIT : integer;
            max_experiment_repetition_counter_value     :   integer;
            max_step_counter_value                      :   integer;
            max_initialization_repetition_counter_value :   integer;
            max_photon_counter_value                    :   integer;

            max_photon_counter_window_pulse_value       :   integer
        );
        port (
            rst                     :   in std_logic;
            clk                     :   in std_logic;
            rx_serial               :   in std_logic;
            trigger_from_awg        :   in std_logic;
            trigger_from_apd        :   in  std_logic;

            flag_start_experiment   :   out std_logic;
            flag_hard_limit         :   out std_logic;
            flag_nv_minus           :   out std_logic;

            trigger_to_awg          :   out std_logic;

            pulse_laser_1           :   out std_logic;
            pulse_laser_2           :   out std_logic;
            pulse_laser_3           :   out std_logic;
            pulse_laser_4           :   out std_logic;

            pulse_htm_dac_1         :   out std_logic;
            pulse_htm_dac_2         :   out std_logic;

            pulse_ni_gate           :   out std_logic
        );
    end component;


begin



    inst_gsr : GSR
        port map(       GSR => GSRN);

    OSCinst0 : OSCH
        port map(       STDBY => '0',
                        OSC => clk,
                        SEDSTDBY => open);

    inst_tiptop_module : tiptop_module
                                        generic map(
                                                    g_CLKS_PER_BIT => 461,
                                                    max_experiment_repetition_counter_value => 100001,
                                                    max_step_counter_value => 133001,
                                                    max_initialization_repetition_counter_value => 257,
                                                    max_photon_counter_value => 513,
                                                    max_photon_counter_window_pulse_value => 133001
                                                    )
                                        port map (
                                                    rst => GSRN,
                                                    clk => clk,

                                                    rx_serial => rx_serial,
                                                    trigger_from_awg => trigger_from_awg,
                                                    trigger_from_apd => trigger_from_apd,

                                                    flag_start_experiment => flag_start_experiment,
                                                    flag_hard_limit => flag_hard_limit,
                                                    flag_nv_minus => flag_nv_minus,

                                                    trigger_to_awg => trigger_to_awg,

                                                    pulse_laser_1 => pulse_laser_1,
                                                    pulse_laser_2 => pulse_laser_2,
                                                    pulse_laser_3 => pulse_laser_3,
                                                    pulse_laser_4 => pulse_laser_4,
                                                    pulse_htm_dac_1 => pulse_htm_dac_1,
                                                    pulse_htm_dac_2 => pulse_htm_dac_2,

                                                    pulse_ni_gate => pulse_ni_gate
                                                    );


end behaviour;