/*
 * AUDIO_SELECTOR_FACTORY.c
 *
 *  Created on: May 3, 2021
 *      Author: Christopher
 */

#include "stm32h753xx.h"
#include "Opcode.h"
#include "I2S_FACTORY.h"

void INPUT_AUDIO_SELECTOR (int INPUT_TYPE, int BIT_RATE, int SAMPLING_RATE) {
    RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN);
    //DECONFIG I2S
    SPI1->CR1 |= SPI_CR1_CSUSP;
    while (((SPI1->CR1) & (SPI_CR1_CSTART)));
    DMA1_Stream0->CR &= ~DMA_SxCR_EN;
    DMA1_Stream1->CR &= ~DMA_SxCR_EN;
    SPI1->CR1 &= ~SPI_CR1_SPE;
    RCC -> CR &= ~(RCC_CR_PLL2ON);

    //CONFIG I2S

    switch (SAMPLING_RATE) {

    case 192000:

        RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
        RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV10);

        RCC -> PLL2FRACR = 0;
        RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_7209);

        RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
                              (RCC_PLLCFGR_PLL2RGE)    |
                              (RCC_PLLCFGR_PLL2FRACEN) |
                              (RCC_PLLCFGR_DIVP2EN)    |
                              (RCC_PLLCFGR_DIVQ2EN)    |
                              (RCC_PLLCFGR_DIVR2EN));

        RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
                            (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
                            (RCC_PLLCFGR_DIVP2EN)               |
                            (RCC_PLLCFGR_PLL2FRACEN);

        RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
                              (RCC_PLL2DIVR_P2));

        RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_122) |
                            (RCC_PLL2DIVR_P2_4);
               break;
    case 96000:

        RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
        RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV10);

        RCC -> PLL2FRACR = 0;
        RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_7209);

        RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
                              (RCC_PLLCFGR_PLL2RGE)    |
                              (RCC_PLLCFGR_PLL2FRACEN) |
                              (RCC_PLLCFGR_DIVP2EN)    |
                              (RCC_PLLCFGR_DIVQ2EN)    |
                              (RCC_PLLCFGR_DIVR2EN));

        RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
                            (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
                            (RCC_PLLCFGR_DIVP2EN)               |
                            (RCC_PLLCFGR_PLL2FRACEN);

        RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
                              (RCC_PLL2DIVR_P2));

        RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_122) |
                            (RCC_PLL2DIVR_P2_8);
              break;
    case 48000:

        RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
        RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV4);

        RCC -> PLL2FRACR = 0;
        RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_1835);

        RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
                              (RCC_PLLCFGR_PLL2RGE)    |
                              (RCC_PLLCFGR_PLL2FRACEN) |
                              (RCC_PLLCFGR_DIVP2EN)    |
                              (RCC_PLLCFGR_DIVQ2EN)    |
                              (RCC_PLLCFGR_DIVR2EN));

        RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
                            (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
                            (RCC_PLLCFGR_DIVP2EN)               |
                            (RCC_PLLCFGR_PLL2FRACEN);

        RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
                              (RCC_PLL2DIVR_P2));

        RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_52) |
                            (RCC_PLL2DIVR_P2_17);
               break;
    case 44100:

        RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
        RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV4);

        RCC -> PLL2FRACR = 0;
        RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_1835);

        RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
                              (RCC_PLLCFGR_PLL2RGE)    |
                              (RCC_PLLCFGR_PLL2FRACEN) |
                              (RCC_PLLCFGR_DIVP2EN)    |
                              (RCC_PLLCFGR_DIVQ2EN)    |
                              (RCC_PLLCFGR_DIVR2EN));

        RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
                            (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
                            (RCC_PLLCFGR_DIVP2EN)               |
                            (RCC_PLLCFGR_PLL2FRACEN);

        RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
                              (RCC_PLL2DIVR_P2));

        RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_28) |
                            (RCC_PLL2DIVR_P2_10);
               break;

    }

    RCC -> D2CCIP1R &= ~(RCC_D2CCIP1R_SPI123SEL);
    RCC -> D2CCIP1R |=  (RCC_D2CCIP1R_SPI123SEL_PLL2_P_CK);

    RCC -> CR &= ~(RCC_CR_PLL2ON);
    RCC -> CR |=  (RCC_CR_PLL2ON);

    while (!((RCC -> CR) & (RCC_CR_PLL2RDY)));


    SPI1->I2SCFGR = 0x00;
    SPI1->CFG1 &= ~((SPI_CFG1_RXDMAEN) |
                    (SPI_CFG1_TXDMAEN));

                     SPI1->CFG1 |= (SPI_CFG1_RXDMAEN) |
                                   (SPI_CFG1_TXDMAEN);
                     SPI1->I2SCFGR |= (SPI_I2SCFGR_MCKOE)              |
                                      (SPI_I2SCFGR_I2SDIV_2)           |
                                      (SPI_I2SCFGR_DATFMT_LEFT)        |
                                      (SPI_I2SCFGR_I2SSTD_I2S)         |
                                      (SPI_I2SCFGR_I2SCFG_MASTER_FULL) |
                                      (SPI_I2SCFGR_I2SMOD_I2S);

    switch (INPUT_TYPE) {

    case INPUT_INLINE:

        /* SPI1->CR1 |= SPI_CR1_CSUSP;
         while (!((SPI1->CR1) & (SPI_CR1_CSTART)));
         DMA1_Stream0->CR &= ~DMA_SxCR_EN;
         DMA1_Stream1->CR &= ~DMA_SxCR_EN;
         SPI1->CR1 &= ~SPI_CR1_SPE; */

        break;


    case INPUT_BLUETOOTH:
         //Disable everything else besides BT
        break;
    }

    switch (BIT_RATE) {

    case 16:
            SPI1->I2SCFGR |= (SPI_I2SCFGR_DATLEN_16BIT);
            SPI1->I2SCFGR |= (SPI_I2SCFGR_CHLEN_32BIT);
            break;

    case 24:
            SPI1->I2SCFGR |= (SPI_I2SCFGR_DATLEN_24BIT);
            SPI1->I2SCFGR |= (SPI_I2SCFGR_CHLEN_32BIT);
            break;

        }

     DMA1_Stream0->CR |= DMA_SxCR_EN;
     //DMA1_Stream1->CR |= DMA_SxCR_EN;
     SPI1->CR1 |= SPI_CR1_SPE;
     SPI1->CR1 |= SPI_CR1_CSTART;
     SET_I2S_INTERRUPT();

}