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Jun 19th, 2019
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VHDL 1.08 KB | None | 0 0
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    11:10:39 06/11/2019
  6. -- Design Name:
  7. -- Module Name:    kropka - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity kropka is
  33.     Port ( wejscie : in  STD_LOGIC_VECTOR (1 downto 0);
  34.            wyjscie : out  STD_LOGIC);
  35. end kropka;
  36.  
  37. architecture Behavioral of kropka is
  38.  
  39. begin
  40.  
  41. with wejscie select
  42.     wyjscie <=      '0' when "01"
  43.                         '1' when others;
  44.  
  45. end Behavioral;
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