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Nov 21st, 2018
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VHDL 0.27 KB | None | 0 0
  1. ResReg: process (div_reset, div_clk)
  2. begin
  3.     if div_reset = '1' then
  4.     CalValdiv_int <= X"00"; --when reset, set Calval to 0
  5.     elsif rising_edge(div_clk) then
  6.     CalValdiv_int <= CalValdiv_int(6 downto 0) & ResLsb; --for each rising clock, shift result.
  7.     end if;
  8. end process;
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