#include <msp430.h>
//  This is a hack of TI example MSP430F55xx_adc_06.c
//  It provides an option ADC_TIMER=1 which will do fixed-rate
//  sampling at (SMCLK/20000)Hz, nominally 50Hz.
//  ACLK=TACLK=32768 Hz; MCLK=SMCLK=default DCO=1.045 Mhz
//  (It can go faster, but this provides for a visible LED blink.)

#define ADC_TIMER_PERIOD 16384      // 32768 Hz/Timer_period = F_sample Hz.(Modificare se necessario)

#define Num_of_Results   1

volatile unsigned int A0results[Num_of_Results];
volatile unsigned int A1results[Num_of_Results];
volatile unsigned int A2results[Num_of_Results];
volatile unsigned int A3results[Num_of_Results];

int main(void)
{
  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer

  P1DIR |= BIT0;
  P1OUT &= ~BIT0;                           // Launchpad LED2=P4.7 (active high)

  P6SEL = 0x0F;                             // Enable A/D channel inputs
  ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_8; // Turn on ADC12, extend sampling time to avoid overflow of results

  ADC12CTL1 = ADC12SHP+ADC12CONSEQ_1;       // Use sampling timer, one burst per trigger
  ADC12CTL2=ADC12RES_0;// 8bit

  ADC12MCTL0 = ADC12INCH_0;                 // ref+=AVcc, channel = A0
  ADC12MCTL1 = ADC12INCH_1;                 // ref+=AVcc, channel = A1
  ADC12MCTL2 = ADC12INCH_2;                 // ref+=AVcc, channel = A2
  ADC12MCTL3 = ADC12INCH_3+ADC12EOS;        // ref+=AVcc, channel = A3, end seq.
  ADC12IE = 0x08;                           // Enable ADC12IFG.3

  //    SLAS590M Table 6-11 shows that ADC12SHS=1 corresponds to
  //    TA0:CCI1B, i.e. a pulse generated via TA0CCR1 on the F5529.
  //    For others, check the data sheet.
  //    This code generates a pulse train with a rising edge halfway
  //    through the period for no particular reason.
  TA0CCTL1 = OUTMOD_3;                      // Set/Reset for rising edge
  TA0CCR1 = ADC_TIMER_PERIOD/2-1;           //   halfway through
  TA0CCR0 = ADC_TIMER_PERIOD-1;             // Cycle every 20000 SMCLKs, i.e. 50Hz.
  ADC12CTL1 |= ADC12SHS_1;                  // SHS=1 means TA0:CCI1B on the F5529
  ADC12CTL0 |= ADC12ENC;                    // Note this locks sundry ADC12 fields.
  TA0CTL = TASSEL_1 | ID_0 | MC_1 | TACLR;  // ACLK, /1, Up (,clear)



  __bis_SR_register(LPM0_bits + GIE);       // Enter LPM0, Enable interrupts
  //__no_operation();                         // For debugger

}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
  static unsigned int index = 0;

  switch(__even_in_range(ADC12IV,34))
  {
  case  0: break;                           // Vector  0:  No interrupt
  case  2: break;                           // Vector  2:  ADC overflow
  case  4: break;                           // Vector  4:  ADC timing overflow
  case  6: break;                           // Vector  6:  ADC12IFG0
  case  8: break;                           // Vector  8:  ADC12IFG1
  case 10: break;                           // Vector 10:  ADC12IFG2
  case 12:                                  // Vector 12:  ADC12IFG3
    A0results[index] = ADC12MEM0;           // Move A0 results, IFG is cleared
    A1results[index] = ADC12MEM1;           // Move A1 results, IFG is cleared
    A2results[index] = ADC12MEM2;           // Move A2 results, IFG is cleared
    A3results[index] = ADC12MEM3;           // Move A3 results, IFG is cleared

    ADC12CTL0 &= ~ADC12ENC;                 // Re-arm burst trigger
    ADC12CTL0 |= ADC12ENC;                  // See also SLAU208P Fig 28-8

    index++;                                // Increment results index, modulo; Set Breakpoint1 here

    if (index == Num_of_Results)
    {
      index = 0;

      P1OUT ^= BIT0;                        // Toggle LED1 Fcamp/num_results/toggle (1Hz/1/2=~0.5Hz)

    }
  case 14: break;                           // Vector 14:  ADC12IFG4
  case 16: break;                           // Vector 16:  ADC12IFG5
  case 18: break;                           // Vector 18:  ADC12IFG6
  case 20: break;                           // Vector 20:  ADC12IFG7
  case 22: break;                           // Vector 22:  ADC12IFG8
  case 24: break;                           // Vector 24:  ADC12IFG9
  case 26: break;                           // Vector 26:  ADC12IFG10
  case 28: break;                           // Vector 28:  ADC12IFG11
  case 30: break;                           // Vector 30:  ADC12IFG12
  case 32: break;                           // Vector 32:  ADC12IFG13
  case 34: break;                           // Vector 34:  ADC12IFG14
  default: break;
  }
}