code_lock_tester

------ code_lock_tester ------
library ieee;
use ieee.std_logic_1164.all;

entity code_lock_tester is
port(
    CLOCK_50        : in std_logic;
    KEY             : in std_logic_vector(1 downto 0);
    SW              : in std_logic_vector(3 downto 0);
    LEDG0, LEDR0    : out std_logic;
    HEX0            : out std_logic_vector(6 downto 0));
end code_lock_tester;


architecture structural of code_lock_tester is
    signal hex : std_logic_vector(3 downto 0);
begin

I1: entity work.code_lock
     port map(
     clk        => CLOCK_50,
     reset      => KEY(1),
     code       => SW,
     enter      => KEY(0),
     lock       => LEDG0,
     err        => LEDR0,
     err_hex    => hex);

I2: entity work.bin2hex -- HEX display til antal errors
     port map(
     bin        => hex,
     seg        => HEX0);

end structural;