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Oct 31st, 2019
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  1. void RCC_init(void){
  2.       // Enable external oscillator
  3.     RCC->CR |= RCC_CR_HSEON;
  4.       while(!(RCC->CR & RCC_CR_HSERDY));
  5.    
  6.       // Config FLASH (?) source - youtube: Nordic Energy
  7.       FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY;
  8.    
  9.       // Manual disable PLL before config, just in case
  10.       RCC->CR &= ~RCC_CR_PLLON;
  11.       while((RCC->CR & RCC_CR_PLLRDY));
  12.    
  13.       // Set all CFGR bits to 0
  14.       RCC->PLLCFGR &= RCC_PLLCFGR_PLLM;
  15.       RCC->PLLCFGR &= RCC_PLLCFGR_PLLN;
  16.       RCC->PLLCFGR &= RCC_PLLCFGR_PLLP;
  17.    
  18.       // Config PLL
  19.       RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE; // source - HSE
  20.       RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_2;     // divide for 4 (second bit to 1)000100 = 4 8MHz/4=2MHz
  21.       RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7; // multiply for 200 011001000 2MHz*200=400MHz
  22.       RCC->PLLCFGR |= RCC_PLLCFGR_PLLP_0; // set PLLP to 4 400MHz/4 = 100MHz
  23.    
  24.       RCC->CFGR = RCC_CFGR_HPRE_DIV1;  // AHB = SYSCLK/1 =100MHz
  25.       RCC->CFGR = RCC_CFGR_PPRE1_DIV4; // APB1 = HCLK/4 =25MHz
  26.       RCC->CFGR = RCC_CFGR_PPRE2_DIV2; // APB2 = HCLK/2 =50MHz
  27.    
  28.       // Enable PLL
  29.       RCC->CR |= RCC_CR_PLLON;
  30.       while(!(RCC->CR & RCC_CR_PLLRDY));   
  31.      
  32.      
  33.         // Set PLL as system clock
  34.         RCC->CFGR &= ~RCC_CFGR_SW;
  35.         RCC->CFGR |= RCC_CFGR_SW_PLL;
  36.         while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1);   
  37. }
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