Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- void RCC_init(void){
- // Enable external oscillator
- RCC->CR |= RCC_CR_HSEON;
- while(!(RCC->CR & RCC_CR_HSERDY));
- // Config FLASH (?) source - youtube: Nordic Energy
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY;
- // Manual disable PLL before config, just in case
- RCC->CR &= ~RCC_CR_PLLON;
- while((RCC->CR & RCC_CR_PLLRDY));
- // Set all CFGR bits to 0
- RCC->PLLCFGR &= RCC_PLLCFGR_PLLM;
- RCC->PLLCFGR &= RCC_PLLCFGR_PLLN;
- RCC->PLLCFGR &= RCC_PLLCFGR_PLLP;
- // Config PLL
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE; // source - HSE
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_2; // divide for 4 (second bit to 1)000100 = 4 8MHz/4=2MHz
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7; // multiply for 200 011001000 2MHz*200=400MHz
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLP_0; // set PLLP to 4 400MHz/4 = 100MHz
- RCC->CFGR = RCC_CFGR_HPRE_DIV1; // AHB = SYSCLK/1 =100MHz
- RCC->CFGR = RCC_CFGR_PPRE1_DIV4; // APB1 = HCLK/4 =25MHz
- RCC->CFGR = RCC_CFGR_PPRE2_DIV2; // APB2 = HCLK/2 =50MHz
- // Enable PLL
- RCC->CR |= RCC_CR_PLLON;
- while(!(RCC->CR & RCC_CR_PLLRDY));
- // Set PLL as system clock
- RCC->CFGR &= ~RCC_CFGR_SW;
- RCC->CFGR |= RCC_CFGR_SW_PLL;
- while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1);
- }
Advertisement
Add Comment
Please, Sign In to add comment