RelogiosP2

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity relogios is
port (
    clk50mhz:   in STD_LOGIC;
    clk2e1, clk2e2, clk2e3, clk2e4: out STD_LOGIC
);
end relogios;

architecture rtl of relogios is
    signal count2e4: INTEGER :=1250 - 1 ; -- para 20000Hz 5e7/2e4 * 1/2 = 2500/2  ; o um garante que a contagem não ultrapasse o valor desejado
    signal count10: INTEGER :=5 - 1; -- Para dividir o clock em 10, implementado de forma a cada 5 passagens do original alternar o valor

    signal value2e1: INTEGER range 0 to 5;
    signal value2e2: INTEGER range 0 to 5;
    signal value2e3: INTEGER range 0 to 5;
    signal value2e4: INTEGER range 0 to 1250;

    signal clk_state2e1: STD_LOGIC := '0';
    signal clk_state2e2: STD_LOGIC := '0';
    signal clk_state2e3: STD_LOGIC := '0';
    signal clk_state2e4: STD_LOGIC := '0';

begin

    -- Gerando clock de 20000Hz a partir do clock original de 50MHz
    gen_clock2e4: process(clk50mhz, clk_state2e4)
    begin
        if clk50mhz'event and clk50mhz='1' then
            if value2e4 < count2e4 then
                value2e4 <= value2e4+1;
            else
                clk_state2e4 <= not clk_state2e4;
                value2e4 <= 0;
            end if;
        end if;
    end process;


    --Gerando clock de 2000Hz a partir do clock de 20000Hz
    gen_clock2e3: process(clk_state2e4)
    begin
        if clk_state2e4'event and clk_state2e4='1' then
            if value2e3 < count10 then
                value2e3 <= value2e3+1;
            else
                clk_state2e3 <= not clk_state2e3;
                value2e3 <= 0;
            end if;
        end if;
    end process;


    --Gerando clock de 200Hz a partir do clock de 2000Hz
    gen_clock2e2: process(clk_state2e3)
    begin
        if clk_state2e3'event and clk_state2e3='1' then
            if value2e2 < count10 then
                value2e2 <= value2e2+1;
            else
                clk_state2e2 <= not clk_state2e2;
                value2e2 <= 0;
            end if;
        end if;
    end process;

    --Gerando clock de 20Hz a partir do clock de 200Hz
    gen_clock2e1: process(clk_state2e2)
    begin
        if clk_state2e2'event and clk_state2e2='1' then
            if value2e1 < count10 then
                value2e1 <= value2e1+1;
            else
                clk_state2e1 <= not clk_state2e1;
                value2e1 <= 0;
            end if;
        end if;
    end process;



    clk2e1 <= clk_state2e1;
    clk2e2 <= clk_state2e2;
    clk2e3 <= clk_state2e3;
    clk2e4 <= clk_state2e4;

end rtl;